CIRCT  19.0.0git
SVPasses.h
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1 //===- SVPasses.h - SV pass entry points ------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This header file defines prototypes that expose pass constructors.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef CIRCT_DIALECT_SV_SVPASSES_H
14 #define CIRCT_DIALECT_SV_SVPASSES_H
15 
16 #include "mlir/Pass/Pass.h"
17 #include "llvm/ADT/StringRef.h"
18 
19 namespace circt {
20 namespace sv {
21 
22 #define GEN_PASS_DECL_HWELIMINATEINOUTPORTS
23 #include "circt/Dialect/SV/SVPasses.h.inc"
24 
25 std::unique_ptr<mlir::Pass> createPrettifyVerilogPass();
26 std::unique_ptr<mlir::Pass> createHWCleanupPass(bool mergeAlwaysBlocks = true);
27 std::unique_ptr<mlir::Pass> createHWStubExternalModulesPass();
28 std::unique_ptr<mlir::Pass> createHWLegalizeModulesPass();
29 std::unique_ptr<mlir::Pass> createSVTraceIVerilogPass();
30 std::unique_ptr<mlir::Pass> createHWLowerInstanceChoices();
31 std::unique_ptr<mlir::Pass> createHWGeneratorCalloutPass();
32 std::unique_ptr<mlir::Pass> createHWEliminateInOutPortsPass(
33  const HWEliminateInOutPortsOptions &options = {});
34 std::unique_ptr<mlir::Pass>
35 createSVExtractTestCodePass(bool disableInstanceExtraction = false,
36  bool disableRegisterExtraction = false,
37  bool disableModuleInlining = false);
38 std::unique_ptr<mlir::Pass> createHWExportModuleHierarchyPass();
39 /// Generate the code for registering passes.
40 #define GEN_PASS_REGISTRATION
41 #include "circt/Dialect/SV/SVPasses.h.inc"
42 
43 } // namespace sv
44 } // namespace circt
45 
46 #endif // CIRCT_DIALECT_SV_SVPASSES_H
std::unique_ptr< mlir::Pass > createSVTraceIVerilogPass()
std::unique_ptr< mlir::Pass > createHWExportModuleHierarchyPass()
std::unique_ptr< mlir::Pass > createSVExtractTestCodePass(bool disableInstanceExtraction=false, bool disableRegisterExtraction=false, bool disableModuleInlining=false)
std::unique_ptr< mlir::Pass > createHWLegalizeModulesPass()
std::unique_ptr< mlir::Pass > createHWStubExternalModulesPass()
std::unique_ptr< mlir::Pass > createHWLowerInstanceChoices()
std::unique_ptr< mlir::Pass > createHWEliminateInOutPortsPass(const HWEliminateInOutPortsOptions &options={})
std::unique_ptr< mlir::Pass > createHWGeneratorCalloutPass()
std::unique_ptr< mlir::Pass > createPrettifyVerilogPass()
std::unique_ptr< mlir::Pass > createHWCleanupPass(bool mergeAlwaysBlocks=true)
Definition: HWCleanup.cpp:245
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
Definition: DebugAnalysis.h:21
Definition: sv.py:1