CIRCT  18.0.0git
ESIStdServices.cpp
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1 //===- ESIStdServices.cpp - ESI standard services -------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
13 #include "circt/Dialect/HW/HWOps.h"
14 
15 #include "mlir/IR/BuiltinTypes.h"
16 #include "mlir/IR/ImplicitLocOpBuilder.h"
17 
18 #include <map>
19 #include <memory>
20 
21 using namespace circt;
22 using namespace circt::esi;
23 
24 /// Utility function to create a req/resp pair bundle service port.
25 static ServicePortInfo createReqResp(StringAttr sym, Twine name,
26  StringRef reqName, Type reqType,
27  StringRef respName, Type respType) {
28  assert(reqType && respType);
29  auto *ctxt = reqType ? reqType.getContext() : respType.getContext();
30  auto bundle = ChannelBundleType::get(
31  ctxt,
32  {BundledChannel{StringAttr::get(ctxt, reqName), ChannelDirection::to,
33  ChannelType::get(ctxt, reqType)},
34  BundledChannel{StringAttr::get(ctxt, respName), ChannelDirection::from,
35  ChannelType::get(ctxt, respType)}},
36  /*resettable=false*/ UnitAttr());
37  return {hw::InnerRefAttr::get(sym, StringAttr::get(ctxt, name)),
39 }
40 
41 ServicePortInfo RandomAccessMemoryDeclOp::writePortInfo() {
42  auto *ctxt = getContext();
43  auto addressType = IntegerType::get(ctxt, llvm::Log2_64_Ceil(getDepth()));
44 
45  // Write port
46  hw::StructType writeType = hw::StructType::get(
47  ctxt,
48  {hw::StructType::FieldInfo{StringAttr::get(ctxt, "address"), addressType},
49  hw::StructType::FieldInfo{StringAttr::get(ctxt, "data"),
50  getInnerType()}});
51  return createReqResp(getSymNameAttr(), "write", "req", writeType, "ack",
52  IntegerType::get(ctxt, 0));
53 }
54 
55 ServicePortInfo RandomAccessMemoryDeclOp::readPortInfo() {
56  auto *ctxt = getContext();
57  auto addressType = IntegerType::get(ctxt, llvm::Log2_64_Ceil(getDepth()));
58 
59  return createReqResp(getSymNameAttr(), "read", "address", addressType, "data",
60  getInnerType());
61 }
62 
64  SmallVectorImpl<ServicePortInfo> &ports) {
65  ports.push_back(writePortInfo());
66  ports.push_back(readPortInfo());
67 }
assert(baseType &&"element must be base type")
static ServicePortInfo createReqResp(StringAttr sym, Twine name, StringRef reqName, Type reqType, StringRef respName, Type respType)
Utility function to create a req/resp pair bundle service port.
static SmallVector< PortInfo > getPortList(ModuleTy &mod)
Definition: HWOps.cpp:1382
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
Definition: CalyxOps.cpp:53
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
Definition: DebugAnalysis.h:21
Describes a service port.
Definition: ESIOps.h:31