14 #ifndef CIRCT_DIALECT_FIRRTL_OP_INTERFACES_H
15 #define CIRCT_DIALECT_FIRRTL_OP_INTERFACES_H
22 #include "mlir/IR/Attributes.h"
23 #include "mlir/IR/BuiltinTypes.h"
24 #include "mlir/IR/OpDefinition.h"
25 #include "mlir/IR/SymbolTable.h"
26 #include "llvm/ADT/TypeSwitch.h"
29 class PatternRewriter;
45 hw::InnerSymAttr
sym = {};
66 std::optional<Location> location = {},
67 std::optional<AnnotationSet> annos = {})
102 ::mlir::PatternRewriter *rewriter =
nullptr);
116 function_ref<InFlightDiagnostic()> emitError);
122 #include "circt/Dialect/FIRRTL/FIRRTLOpInterfaces.h.inc"
This class provides a read-only projection over the MLIR attributes that represent a set of annotatio...
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
ClassType getInstanceTypeForClassLike(ClassLike classOp)
LogicalResult verifyForceableOp(Forceable op)
Verify a Forceable op.
LogicalResult verifyTypeAgainstClassLike(ClassLike classOp, ClassType type, function_ref< InFlightDiagnostic()> emitError)
Assuming that the classOp is the source of truth, verify that the type accurately matches the signatu...
Forceable replaceWithNewForceability(Forceable op, bool forceable, ::mlir::PatternRewriter *rewriter=nullptr)
Replace a Forceable op with equivalent, changing whether forceable.
RefType getForceableResultType(bool forceable, Type type)
Return null or forceable reference result type.
Direction
This represents the direction of a single port.
LogicalResult verifyModuleLikeOpInterface(FModuleLike module)
Verification hook for verifying module like operations.
@ LastConnect
Classic FIRRTL connections: last connect 'wins' across paths; conditionally applied under 'when'.
@ StaticSingleConnect
Exclusive connection to the destination, unconditional.
bool isTypeInOut(mlir::Type type)
Returns true if the given type has some flipped (aka unaligned) dataflow.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
This holds the name and type that describes the module's ports.
bool isOutput() const
Return true if this is a simple output-only port.
PortInfo(StringAttr name, Type type, Direction dir, hw::InnerSymAttr sym, Location loc, AnnotationSet annos)
AnnotationSet annotations
PortInfo(StringAttr name, Type type, Direction dir, StringAttr symName={}, std::optional< Location > location={}, std::optional< AnnotationSet > annos={})
Default constructors.
StringRef getName() const
bool isInput() const
Return true if this is a simple input-only port.
bool isInOut() const
Return true if this is an inout port.