13 #ifndef CIRCT_DIALECT_HW_HWOPINTERFACES_H
14 #define CIRCT_DIALECT_HW_HWOPINTERFACES_H
21 #include "mlir/IR/OpDefinition.h"
22 #include "mlir/IR/SymbolTable.h"
29 TypeConverter &converter);
39 InnerSymAttr
sym = {};
41 LocationAttr
loc = {};
52 raw_ostream &
operator<<(raw_ostream &printer, PortInfo port);
69 using iterator = SmallVector<PortInfo>::iterator;
84 std::function<bool(
const PortInfo &)> predicateFn;
86 predicateFn = [](
const PortInfo &port) ->
bool {
91 predicateFn = [](
const PortInfo &port) ->
bool {
95 return llvm::make_filter_range(
ports, predicateFn);
99 std::function<bool(
const PortInfo &)> predicateFn;
101 predicateFn = [](
const PortInfo &port) ->
bool {
106 predicateFn = [](
const PortInfo &port) ->
bool {
110 return llvm::make_filter_range(
ports, predicateFn);
128 return std::distance(r.begin(), r.end());
132 return std::distance(r.begin(), r.end());
137 while (idx ||
ports[port].isOutput()) {
138 if (!
ports[port].isOutput())
147 while (idx || !
ports[port].isOutput()) {
148 if (
ports[port].isOutput())
175 for (
auto &p :
ports)
176 if (
auto inout = dyn_cast<hw::InOutType>(p.type)) {
177 p.type = inout.getElementType();
190 StringAttr name)
const {
191 auto it = portMap.find(name);
192 if (it == portMap.end())
232 class InnerSymbolOpInterface;
246 static bool classof(mlir::Operation *op);
248 static bool classof(
const mlir::RegisteredOperationName *opInfo);
259 template <
typename ConcreteType>
264 ConcreteType::template hasTrait<::mlir::OpTrait::SymbolTable>(),
265 "expected operation to be a SymbolTable");
267 if (op->getNumRegions() != 1)
268 return op->emitError(
"expected operation to have a single region");
269 if (!op->getRegion(0).hasOneBlock())
270 return op->emitError(
"expected operation to have a single block");
278 template <
typename ConcreteType>
285 ConcreteType::template hasTrait<::mlir::SymbolOpInterface::Trait>(),
286 "expected operation to define a Symbol");
289 auto *parent = op->getParentOp();
290 if (!parent || !isa<circt::hw::InnerRefNamespaceLike>(parent))
291 return op->emitError(
292 "InnerSymbolTable must have InnerRefNamespace parent");
300 #include "circt/Dialect/HW/HWOpInterfaces.h.inc"
assert(baseType &&"element must be base type")
llvm::SmallVector< StringAttr > inputs
llvm::SmallVector< StringAttr > outputs
This trait is for operations that define a scope for resolving InnerRef's, and provides verification ...
static LogicalResult verifyRegionTrait(Operation *op)
A trait for inner symbol table functionality on an operation.
static LogicalResult verifyRegionTrait(Operation *op)
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
LogicalResult verifyInnerRefNamespace(Operation *op)
raw_ostream & operator<<(raw_ostream &printer, PortInfo port)
void populateHWModuleLikeTypeConversionPattern(StringRef moduleLikeOpName, RewritePatternSet &patterns, TypeConverter &converter)
LogicalResult verifyInnerSymAttr(InnerSymbolOpInterface op)
Verification hook for verifying InnerSym Attribute.
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
Classify operations that are InnerRefNamespace-like, until structure is in place to do this via Trait...
static bool classof(mlir::Operation *op)
Return if this operation is explicitly an IRN or appears compatible.
This holds a decoded list of input/inout and output ports for a module or instance.
const PortInfo & at(size_t idx) const
const PortInfo & atInput(size_t idx) const
ModulePortInfo(ArrayRef< PortInfo > inputs, ArrayRef< PortInfo > outputs)
size_t portNumForInput(size_t idx) const
llvm::iterator_range< llvm::filter_iterator< iterator, std::function< bool(const PortInfo &)> >> PortDirectionRange
size_t portNumForOutput(size_t idx) const
size_t sizeOutputs() const
ConstPortDirectionRange getPortsOfDirection(bool input) const
llvm::iterator_range< llvm::filter_iterator< const_iterator, std::function< bool(const PortInfo &)> >> ConstPortDirectionRange
SmallVector< PortInfo > ports
This contains a list of all ports. Input first.
PortInfo & at(size_t idx)
ConstPortDirectionRange getOutputs() const
SmallVector< PortInfo >::const_iterator const_iterator
const PortInfo & atOutput(size_t idx) const
SmallVector< PortInfo >::iterator iterator
const_iterator begin() const
PortInfo & atInput(size_t idx)
size_t sizeInputs() const
const_iterator end() const
ConstPortDirectionRange getInputs() const
void eraseInput(size_t idx)
PortDirectionRange getPortsOfDirection(bool input)
PortInfo & atOutput(size_t idx)
PortDirectionRange getInputs()
PortDirectionRange getOutputs()
ModulePortInfo(ArrayRef< PortInfo > mergedPorts)
llvm::DenseMap< StringAttr, unsigned > inputPortMap
llvm::DenseMap< StringAttr, unsigned > outputPortMap
FailureOr< unsigned > getOutputPortIndex(StringRef name) const
FailureOr< unsigned > getInputPortIndex(StringAttr name) const
FailureOr< unsigned > lookupPortIndex(const llvm::DenseMap< StringAttr, unsigned > &portMap, StringAttr name) const
ModulePortLookupInfo(MLIRContext *ctx, const ModulePortInfo &portInfo)
FailureOr< unsigned > getInputPortIndex(StringRef name) const
FailureOr< unsigned > getOutputPortIndex(StringAttr name) const
This holds the name, type, direction of a module's ports.
ssize_t getId() const
Return a unique numeric identifier for this port.
StringRef getName() const
size_t argNum
This is the argument index or the result index depending on the direction.
InnerSymAttr sym
The optional symbol for this port.