CIRCT  20.0.0git
LowerMemory.cpp
Go to the documentation of this file.
1 //===- LowerMemory.cpp - Lower Memories -------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //===----------------------------------------------------------------------===//
7 //
8 // This file defines the LowerMemories pass.
9 //
10 //===----------------------------------------------------------------------===//
11 
18 #include "circt/Dialect/HW/HWOps.h"
21 #include "mlir/IR/Dominance.h"
22 #include "mlir/Pass/Pass.h"
23 #include "llvm/ADT/DepthFirstIterator.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/STLFunctionalExtras.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/Support/Parallel.h"
28 #include <optional>
29 #include <set>
30 
31 namespace circt {
32 namespace firrtl {
33 #define GEN_PASS_DEF_LOWERMEMORY
34 #include "circt/Dialect/FIRRTL/Passes.h.inc"
35 } // namespace firrtl
36 } // namespace circt
37 
38 using namespace circt;
39 using namespace firrtl;
40 
41 // Extract all the relevant attributes from the MemOp and return the FirMemory.
42 FirMemory getSummary(MemOp op) {
43  size_t numReadPorts = 0;
44  size_t numWritePorts = 0;
45  size_t numReadWritePorts = 0;
47  SmallVector<int32_t> writeClockIDs;
48 
49  for (size_t i = 0, e = op.getNumResults(); i != e; ++i) {
50  auto portKind = op.getPortKind(i);
51  if (portKind == MemOp::PortKind::Read)
52  ++numReadPorts;
53  else if (portKind == MemOp::PortKind::Write) {
54  for (auto *a : op.getResult(i).getUsers()) {
55  auto subfield = dyn_cast<SubfieldOp>(a);
56  if (!subfield || subfield.getFieldIndex() != 2)
57  continue;
58  auto clockPort = a->getResult(0);
59  for (auto *b : clockPort.getUsers()) {
60  if (auto connect = dyn_cast<FConnectLike>(b)) {
61  if (connect.getDest() == clockPort) {
62  auto result =
63  clockToLeader.insert({connect.getSrc(), numWritePorts});
64  if (result.second) {
65  writeClockIDs.push_back(numWritePorts);
66  } else {
67  writeClockIDs.push_back(result.first->second);
68  }
69  }
70  }
71  }
72  break;
73  }
74  ++numWritePorts;
75  } else
76  ++numReadWritePorts;
77  }
78 
79  auto width = op.getDataType().getBitWidthOrSentinel();
80  if (width <= 0) {
81  op.emitError("'firrtl.mem' should have simple type and known width");
82  width = 0;
83  }
84  return {numReadPorts,
85  numWritePorts,
86  numReadWritePorts,
87  (size_t)width,
88  op.getDepth(),
89  op.getReadLatency(),
90  op.getWriteLatency(),
91  op.getMaskBits(),
92  *seq::symbolizeRUW(unsigned(op.getRuw())),
93  seq::WUW::PortOrder,
94  writeClockIDs,
95  op.getNameAttr(),
96  op.getMaskBits() > 1,
97  op.getInitAttr(),
98  op.getPrefixAttr(),
99  op.getLoc()};
100 }
101 
102 namespace {
103 struct LowerMemoryPass
104  : public circt::firrtl::impl::LowerMemoryBase<LowerMemoryPass> {
105 
106  /// Get the cached namespace for a module.
107  hw::InnerSymbolNamespace &getModuleNamespace(FModuleLike moduleOp) {
108  return moduleNamespaces.try_emplace(moduleOp, moduleOp).first->second;
109  }
110 
111  SmallVector<PortInfo> getMemoryModulePorts(const FirMemory &mem);
112  FMemModuleOp emitMemoryModule(MemOp op, const FirMemory &summary,
113  const SmallVectorImpl<PortInfo> &ports);
114  FMemModuleOp getOrCreateMemModule(MemOp op, const FirMemory &summary,
115  const SmallVectorImpl<PortInfo> &ports,
116  bool shouldDedup);
117  FModuleOp createWrapperModule(MemOp op, const FirMemory &summary,
118  bool shouldDedup);
119  InstanceOp emitMemoryInstance(MemOp op, FModuleOp moduleOp,
120  const FirMemory &summary);
121  void lowerMemory(MemOp mem, const FirMemory &summary, bool shouldDedup);
122  LogicalResult runOnModule(FModuleOp moduleOp, bool shouldDedup);
123  void runOnOperation() override;
124 
125  /// Cached module namespaces.
126  DenseMap<Operation *, hw::InnerSymbolNamespace> moduleNamespaces;
127  CircuitNamespace circuitNamespace;
128  SymbolTable *symbolTable;
129 
130  /// The set of all memories seen so far. This is used to "deduplicate"
131  /// memories by emitting modules one module for equivalent memories.
132  std::map<FirMemory, FMemModuleOp> memories;
133 
134  /// A sequence of operations that should be erased later.
135  SetVector<Operation *> operationsToErase;
136 };
137 } // end anonymous namespace
138 
139 SmallVector<PortInfo>
140 LowerMemoryPass::getMemoryModulePorts(const FirMemory &mem) {
141  auto *context = &getContext();
142 
143  // We don't need a single bit mask, it can be combined with enable. Create
144  // an unmasked memory if maskBits = 1.
145  FIRRTLType u1Type = UIntType::get(context, 1);
146  FIRRTLType dataType = UIntType::get(context, mem.dataWidth);
147  FIRRTLType maskType = UIntType::get(context, mem.maskBits);
148  FIRRTLType addrType =
149  UIntType::get(context, std::max(1U, llvm::Log2_64_Ceil(mem.depth)));
150  FIRRTLType clockType = ClockType::get(context);
151  Location loc = UnknownLoc::get(context);
152  AnnotationSet annotations = AnnotationSet(context);
153 
154  SmallVector<PortInfo> ports;
155  auto addPort = [&](const Twine &name, FIRRTLType type, Direction direction) {
156  auto nameAttr = StringAttr::get(context, name);
157  ports.push_back(
158  {nameAttr, type, direction, hw::InnerSymAttr{}, loc, annotations});
159  };
160 
161  auto makePortCommon = [&](StringRef prefix, size_t idx, FIRRTLType addrType) {
162  addPort(prefix + Twine(idx) + "_addr", addrType, Direction::In);
163  addPort(prefix + Twine(idx) + "_en", u1Type, Direction::In);
164  addPort(prefix + Twine(idx) + "_clk", clockType, Direction::In);
165  };
166 
167  for (size_t i = 0, e = mem.numReadPorts; i != e; ++i) {
168  makePortCommon("R", i, addrType);
169  addPort("R" + Twine(i) + "_data", dataType, Direction::Out);
170  }
171  for (size_t i = 0, e = mem.numReadWritePorts; i != e; ++i) {
172  makePortCommon("RW", i, addrType);
173  addPort("RW" + Twine(i) + "_wmode", u1Type, Direction::In);
174  addPort("RW" + Twine(i) + "_wdata", dataType, Direction::In);
175  addPort("RW" + Twine(i) + "_rdata", dataType, Direction::Out);
176  // Ignore mask port, if maskBits =1
177  if (mem.isMasked)
178  addPort("RW" + Twine(i) + "_wmask", maskType, Direction::In);
179  }
180 
181  for (size_t i = 0, e = mem.numWritePorts; i != e; ++i) {
182  makePortCommon("W", i, addrType);
183  addPort("W" + Twine(i) + "_data", dataType, Direction::In);
184  // Ignore mask port, if maskBits =1
185  if (mem.isMasked)
186  addPort("W" + Twine(i) + "_mask", maskType, Direction::In);
187  }
188 
189  return ports;
190 }
191 
192 FMemModuleOp
193 LowerMemoryPass::emitMemoryModule(MemOp op, const FirMemory &mem,
194  const SmallVectorImpl<PortInfo> &ports) {
195  // Get a non-colliding name for the memory module, and update the summary.
196  auto newName = circuitNamespace.newName(mem.modName.getValue(), "ext");
197  auto moduleName = StringAttr::get(&getContext(), newName);
198 
199  // Insert the memory module just above the current module.
200  OpBuilder b(op->getParentOfType<FModuleOp>());
201  ++numCreatedMemModules;
202  auto moduleOp = b.create<FMemModuleOp>(
203  mem.loc, moduleName, ports, mem.numReadPorts, mem.numWritePorts,
204  mem.numReadWritePorts, mem.dataWidth, mem.maskBits, mem.readLatency,
205  mem.writeLatency, mem.depth);
206  SymbolTable::setSymbolVisibility(moduleOp, SymbolTable::Visibility::Private);
207  return moduleOp;
208 }
209 
210 FMemModuleOp
211 LowerMemoryPass::getOrCreateMemModule(MemOp op, const FirMemory &summary,
212  const SmallVectorImpl<PortInfo> &ports,
213  bool shouldDedup) {
214  // Try to find a matching memory blackbox that we already created. If
215  // shouldDedup is true, we will just generate a new memory module.
216  if (shouldDedup) {
217  auto it = memories.find(summary);
218  if (it != memories.end())
219  return it->second;
220  }
221 
222  // Create a new module for this memory. This can update the name recorded in
223  // the memory's summary.
224  auto moduleOp = emitMemoryModule(op, summary, ports);
225 
226  // Record the memory module. We don't want to use this module for other
227  // memories, then we don't add it to the table.
228  if (shouldDedup)
229  memories[summary] = moduleOp;
230 
231  return moduleOp;
232 }
233 
234 void LowerMemoryPass::lowerMemory(MemOp mem, const FirMemory &summary,
235  bool shouldDedup) {
236  auto *context = &getContext();
237  auto ports = getMemoryModulePorts(summary);
238 
239  // Get a non-colliding name for the memory module, and update the summary.
240  auto newName = circuitNamespace.newName(mem.getName());
241  auto wrapperName = StringAttr::get(&getContext(), newName);
242 
243  // Create the wrapper module, inserting it just before the current module.
244  OpBuilder b(mem->getParentOfType<FModuleOp>());
245  auto wrapper = b.create<FModuleOp>(
246  mem->getLoc(), wrapperName,
247  ConventionAttr::get(context, Convention::Internal), ports);
248  SymbolTable::setSymbolVisibility(wrapper, SymbolTable::Visibility::Private);
249 
250  // Create an instance of the external memory module. The instance has the
251  // same name as the target module.
252  auto memModule = getOrCreateMemModule(mem, summary, ports, shouldDedup);
253  b.setInsertionPointToStart(wrapper.getBodyBlock());
254 
255  auto memInst =
256  b.create<InstanceOp>(mem->getLoc(), memModule, memModule.getModuleName(),
257  mem.getNameKind(), mem.getAnnotations().getValue());
258 
259  // Wire all the ports together.
260  for (auto [dst, src] : llvm::zip(wrapper.getBodyBlock()->getArguments(),
261  memInst.getResults())) {
262  if (wrapper.getPortDirection(dst.getArgNumber()) == Direction::Out)
263  b.create<MatchingConnectOp>(mem->getLoc(), dst, src);
264  else
265  b.create<MatchingConnectOp>(mem->getLoc(), src, dst);
266  }
267 
268  // Create an instance of the wrapper memory module, which will replace the
269  // original mem op.
270  auto inst = emitMemoryInstance(mem, wrapper, summary);
271 
272  // We fixup the annotations here. We will be copying all annotations on to the
273  // module op, so we have to fix up the NLA to have the module as the leaf
274  // element.
275 
276  auto leafSym = memModule.getModuleNameAttr();
277  auto leafAttr = FlatSymbolRefAttr::get(wrapper.getModuleNameAttr());
278 
279  // NLAs that we have already processed.
281  auto nonlocalAttr = StringAttr::get(context, "circt.nonlocal");
282  bool nlaUpdated = false;
283  SmallVector<Annotation> newMemModAnnos;
284  OpBuilder nlaBuilder(context);
285 
286  AnnotationSet::removeAnnotations(memInst, [&](Annotation anno) -> bool {
287  // We're only looking for non-local annotations.
288  auto nlaSym = anno.getMember<FlatSymbolRefAttr>(nonlocalAttr);
289  if (!nlaSym)
290  return false;
291  // If we have already seen this NLA, don't re-process it.
292  auto newNLAIter = processedNLAs.find(nlaSym.getAttr());
293  StringAttr newNLAName;
294  if (newNLAIter == processedNLAs.end()) {
295 
296  // Update the NLA path to have the additional wrapper module.
297  auto nla =
298  dyn_cast<hw::HierPathOp>(symbolTable->lookup(nlaSym.getAttr()));
299  auto namepath = nla.getNamepath().getValue();
300  SmallVector<Attribute> newNamepath(namepath.begin(), namepath.end());
301  if (!nla.isComponent())
302  newNamepath.back() =
303  getInnerRefTo(inst, [&](auto mod) -> hw::InnerSymbolNamespace & {
304  return getModuleNamespace(mod);
305  });
306  newNamepath.push_back(leafAttr);
307 
308  nlaBuilder.setInsertionPointAfter(nla);
309  auto newNLA = cast<hw::HierPathOp>(nlaBuilder.clone(*nla));
310  newNLA.setSymNameAttr(StringAttr::get(
311  context, circuitNamespace.newName(nla.getNameAttr().getValue())));
312  newNLA.setNamepathAttr(ArrayAttr::get(context, newNamepath));
313  newNLAName = newNLA.getNameAttr();
314  processedNLAs[nlaSym.getAttr()] = newNLAName;
315  } else
316  newNLAName = newNLAIter->getSecond();
317  anno.setMember("circt.nonlocal", FlatSymbolRefAttr::get(newNLAName));
318  nlaUpdated = true;
319  newMemModAnnos.push_back(anno);
320  return true;
321  });
322  if (nlaUpdated) {
323  memInst.setInnerSymAttr(hw::InnerSymAttr::get(leafSym));
324  AnnotationSet newAnnos(memInst);
325  newAnnos.addAnnotations(newMemModAnnos);
326  newAnnos.applyToOperation(memInst);
327  }
328  operationsToErase.insert(mem);
329  ++numLoweredMems;
330 }
331 
332 static SmallVector<SubfieldOp> getAllFieldAccesses(Value structValue,
333  StringRef field) {
334  SmallVector<SubfieldOp> accesses;
335  for (auto *op : structValue.getUsers()) {
336  assert(isa<SubfieldOp>(op));
337  auto fieldAccess = cast<SubfieldOp>(op);
338  auto elemIndex =
339  fieldAccess.getInput().getType().base().getElementIndex(field);
340  if (elemIndex && *elemIndex == fieldAccess.getFieldIndex())
341  accesses.push_back(fieldAccess);
342  }
343  return accesses;
344 }
345 
346 InstanceOp LowerMemoryPass::emitMemoryInstance(MemOp op, FModuleOp module,
347  const FirMemory &summary) {
348  OpBuilder builder(op);
349  auto *context = &getContext();
350  auto memName = op.getName();
351  if (memName.empty())
352  memName = "mem";
353 
354  // Process each port in turn.
355  SmallVector<Type, 8> portTypes;
356  SmallVector<Direction> portDirections;
357  SmallVector<Attribute> portNames;
358  DenseMap<Operation *, size_t> returnHolder;
359  mlir::DominanceInfo domInfo(op->getParentOfType<FModuleOp>());
360 
361  // The result values of the memory are not necessarily in the same order as
362  // the memory module that we're lowering to. We need to lower the read
363  // ports before the read/write ports, before the write ports.
364  for (unsigned memportKindIdx = 0; memportKindIdx != 3; ++memportKindIdx) {
365  MemOp::PortKind memportKind = MemOp::PortKind::Read;
366  auto *portLabel = "R";
367  switch (memportKindIdx) {
368  default:
369  break;
370  case 1:
371  memportKind = MemOp::PortKind::ReadWrite;
372  portLabel = "RW";
373  break;
374  case 2:
375  memportKind = MemOp::PortKind::Write;
376  portLabel = "W";
377  break;
378  }
379 
380  // This is set to the count of the kind of memport we're emitting, for
381  // label names.
382  unsigned portNumber = 0;
383 
384  // Get an unsigned type with the specified width.
385  auto getType = [&](size_t width) { return UIntType::get(context, width); };
386  auto ui1Type = getType(1);
387  auto addressType = getType(std::max(1U, llvm::Log2_64_Ceil(summary.depth)));
388  auto dataType = UIntType::get(context, summary.dataWidth);
389  auto clockType = ClockType::get(context);
390 
391  // Memories return multiple structs, one for each port, which means we
392  // have two layers of type to split apart.
393  for (size_t i = 0, e = op.getNumResults(); i != e; ++i) {
394  // Process all of one kind before the next.
395  if (memportKind != op.getPortKind(i))
396  continue;
397 
398  auto addPort = [&](Direction direction, StringRef field, Type portType) {
399  // Map subfields of the memory port to module ports.
400  auto accesses = getAllFieldAccesses(op.getResult(i), field);
401  for (auto a : accesses)
402  returnHolder[a] = portTypes.size();
403  // Record the new port information.
404  portTypes.push_back(portType);
405  portDirections.push_back(direction);
406  portNames.push_back(
407  builder.getStringAttr(portLabel + Twine(portNumber) + "_" + field));
408  };
409 
410  auto getDriver = [&](StringRef field) -> Operation * {
411  auto accesses = getAllFieldAccesses(op.getResult(i), field);
412  for (auto a : accesses) {
413  for (auto *user : a->getUsers()) {
414  // If this is a connect driving a value to the field, return it.
415  if (auto connect = dyn_cast<FConnectLike>(user);
416  connect && connect.getDest() == a)
417  return connect;
418  }
419  }
420  return nullptr;
421  };
422 
423  // Find the value connected to the enable and 'and' it with the mask,
424  // and then remove the mask entirely. This is used to remove the mask when
425  // it is 1 bit.
426  auto removeMask = [&](StringRef enable, StringRef mask) {
427  // Get the connect which drives a value to the mask element.
428  auto *maskConnect = getDriver(mask);
429  if (!maskConnect)
430  return;
431  // Get the connect which drives a value to the en element
432  auto *enConnect = getDriver(enable);
433  if (!enConnect)
434  return;
435  // Find the proper place to create the And operation. The mask and en
436  // signals must both dominate the new operation.
437  OpBuilder b(maskConnect);
438  if (domInfo.dominates(maskConnect, enConnect))
439  b.setInsertionPoint(enConnect);
440  // 'and' the enable and mask signals together and use it as the enable.
441  auto andOp = b.create<AndPrimOp>(
442  op->getLoc(), maskConnect->getOperand(1), enConnect->getOperand(1));
443  enConnect->setOperand(1, andOp);
444  enConnect->moveAfter(andOp);
445  // Erase the old mask connect.
446  auto *maskField = maskConnect->getOperand(0).getDefiningOp();
447  operationsToErase.insert(maskConnect);
448  operationsToErase.insert(maskField);
449  };
450 
451  if (memportKind == MemOp::PortKind::Read) {
452  addPort(Direction::In, "addr", addressType);
453  addPort(Direction::In, "en", ui1Type);
454  addPort(Direction::In, "clk", clockType);
455  addPort(Direction::Out, "data", dataType);
456  } else if (memportKind == MemOp::PortKind::ReadWrite) {
457  addPort(Direction::In, "addr", addressType);
458  addPort(Direction::In, "en", ui1Type);
459  addPort(Direction::In, "clk", clockType);
460  addPort(Direction::In, "wmode", ui1Type);
461  addPort(Direction::In, "wdata", dataType);
462  addPort(Direction::Out, "rdata", dataType);
463  // Ignore mask port, if maskBits =1
464  if (summary.isMasked)
465  addPort(Direction::In, "wmask", getType(summary.maskBits));
466  else
467  removeMask("wmode", "wmask");
468  } else {
469  addPort(Direction::In, "addr", addressType);
470  addPort(Direction::In, "en", ui1Type);
471  addPort(Direction::In, "clk", clockType);
472  addPort(Direction::In, "data", dataType);
473  // Ignore mask port, if maskBits == 1
474  if (summary.isMasked)
475  addPort(Direction::In, "mask", getType(summary.maskBits));
476  else
477  removeMask("en", "mask");
478  }
479 
480  ++portNumber;
481  }
482  }
483 
484  // Create the instance to replace the memop. The instance name matches the
485  // name of the original memory module before deduplication.
486  // TODO: how do we lower port annotations?
487  auto inst = builder.create<InstanceOp>(
488  op.getLoc(), portTypes, module.getNameAttr(), summary.getFirMemoryName(),
489  op.getNameKind(), portDirections, portNames,
490  /*annotations=*/ArrayRef<Attribute>(),
491  /*portAnnotations=*/ArrayRef<Attribute>(),
492  /*layers=*/ArrayRef<Attribute>(), /*lowerToBind=*/false,
493  op.getInnerSymAttr());
494 
495  // Update all users of the result of read ports
496  for (auto [subfield, result] : returnHolder) {
497  subfield->getResult(0).replaceAllUsesWith(inst.getResult(result));
498  operationsToErase.insert(subfield);
499  }
500 
501  return inst;
502 }
503 
504 LogicalResult LowerMemoryPass::runOnModule(FModuleOp moduleOp,
505  bool shouldDedup) {
506  assert(operationsToErase.empty() && "operationsToErase must be empty");
507 
508  auto result = moduleOp.walk([&](MemOp op) {
509  // Check that the memory has been properly lowered already.
510  if (!type_isa<UIntType>(op.getDataType())) {
511  op->emitError("memories should be flattened before running LowerMemory");
512  return WalkResult::interrupt();
513  }
514 
515  auto summary = getSummary(op);
516  if (summary.isSeqMem())
517  lowerMemory(op, summary, shouldDedup);
518 
519  return WalkResult::advance();
520  });
521 
522  if (result.wasInterrupted())
523  return failure();
524 
525  for (Operation *op : operationsToErase)
526  op->erase();
527 
528  operationsToErase.clear();
529 
530  return success();
531 }
532 
533 void LowerMemoryPass::runOnOperation() {
534  auto circuit = getOperation();
535  auto &instanceInfo = getAnalysis<InstanceInfo>();
536  symbolTable = &getAnalysis<SymbolTable>();
537  circuitNamespace.add(circuit);
538 
539  // We iterate the circuit from top-to-bottom. This ensures that we get
540  // consistent memory names. (Memory modules will be inserted before the
541  // module we are processing to prevent these being unnecessarily visited.)
542  // Deduplication of memories is allowed if the module is under the "effective"
543  // design-under-test (DUT).
544  for (auto moduleOp : circuit.getBodyBlock()->getOps<FModuleOp>()) {
545  auto shouldDedup = instanceInfo.anyInstanceUnderEffectiveDut(moduleOp);
546  if (failed(runOnModule(moduleOp, shouldDedup)))
547  return signalPassFailure();
548  }
549 
550  circuitNamespace.clear();
551  symbolTable = nullptr;
552  memories.clear();
553 }
554 
555 std::unique_ptr<mlir::Pass> circt::firrtl::createLowerMemoryPass() {
556  return std::make_unique<LowerMemoryPass>();
557 }
assert(baseType &&"element must be base type")
int32_t width
Definition: FIRRTL.cpp:36
static SmallVector< SubfieldOp > getAllFieldAccesses(Value structValue, StringRef field)
FirMemory getSummary(MemOp op)
Definition: LowerMemory.cpp:42
This class provides a read-only projection over the MLIR attributes that represent a set of annotatio...
bool removeAnnotations(llvm::function_ref< bool(Annotation)> predicate)
Remove all annotations from this annotation set for which predicate returns true.
This class provides a read-only projection of an annotation.
AttrClass getMember(StringAttr name) const
Return a member of the annotation.
void setMember(StringAttr name, Attribute value)
Add or set a member of the annotation to a value.
def connect(destination, source)
Definition: support.py:39
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
Definition: CalyxOps.cpp:55
Direction
This represents the direction of a single port.
hw::InnerRefAttr getInnerRefTo(const hw::InnerSymTarget &target, GetNamespaceCallback getNamespace)
Obtain an inner reference to the target (operation or port), adding an inner symbol as necessary.
std::unique_ptr< mlir::Pass > createLowerMemoryPass()
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
Definition: DebugAnalysis.h:21
The namespace of a CircuitOp, generally inhabited by modules.
Definition: Namespace.h:24
bool isSeqMem() const
Check whether the memory is a seq mem.
Definition: FIRRTLOps.h:234
StringAttr getFirMemoryName() const
Definition: FIRRTLOps.cpp:3335