CIRCT  20.0.0git
LowerCHIRRTL.cpp
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1 //===- LowerCHIRRTL.cpp -----------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //===----------------------------------------------------------------------===//
7 //
8 // Transform CHIRRTL memory operations and memory ports into standard FIRRTL
9 // memory operations.
10 //
11 //===----------------------------------------------------------------------===//
12 
19 #include "circt/Support/LLVM.h"
20 #include "mlir/IR/ImplicitLocOpBuilder.h"
21 #include "mlir/IR/OperationSupport.h"
22 #include "mlir/Pass/Pass.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/Hashing.h"
25 #include "llvm/ADT/TypeSwitch.h"
26 
27 namespace circt {
28 namespace firrtl {
29 #define GEN_PASS_DEF_LOWERCHIRRTLPASS
30 #include "circt/Dialect/FIRRTL/Passes.h.inc"
31 } // namespace firrtl
32 } // namespace circt
33 
34 using namespace circt;
35 using namespace firrtl;
36 using namespace chirrtl;
37 
38 namespace {
39 struct LowerCHIRRTLPass
40  : public circt::firrtl::impl::LowerCHIRRTLPassBase<LowerCHIRRTLPass>,
41  public CHIRRTLVisitor<LowerCHIRRTLPass>,
42  public FIRRTLVisitor<LowerCHIRRTLPass> {
43 
47 
48  void visitCHIRRTL(CombMemOp op);
49  void visitCHIRRTL(SeqMemOp op);
50  void visitCHIRRTL(MemoryPortOp op);
51  void visitCHIRRTL(MemoryDebugPortOp op);
52  void visitCHIRRTL(MemoryPortAccessOp op);
53  void visitExpr(SubaccessOp op);
54  void visitExpr(SubfieldOp op);
55  void visitExpr(SubindexOp op);
56  void visitStmt(ConnectOp op);
57  void visitStmt(MatchingConnectOp op);
58  void visitUnhandledOp(Operation *op);
59 
60  // Chain the CHIRRTL visitor to the FIRRTL visitor.
61  void visitInvalidCHIRRTL(Operation *op) { dispatchVisitor(op); }
62  void visitUnhandledCHIRRTL(Operation *op) { visitUnhandledOp(op); }
63 
64  /// Get a the constant 0. This constant is inserted at the beginning of the
65  /// module.
66  Value getConst(unsigned c) {
67  auto &value = constCache[c];
68  if (!value) {
69  auto module = getOperation();
70  auto builder = OpBuilder::atBlockBegin(module.getBodyBlock());
71  auto u1Type = UIntType::get(builder.getContext(), /*width*/ 1);
72  value = builder.create<ConstantOp>(module.getLoc(), u1Type, APInt(1, c));
73  }
74  return value;
75  }
76 
77  //// Clear out any stale data.
78  void clear() {
79  constCache.clear();
80  invalidCache.clear();
81  opsToDelete.clear();
82  subfieldDirs.clear();
83  rdataValues.clear();
84  wdataValues.clear();
85  }
86 
87  void emitInvalid(ImplicitLocOpBuilder &builder, Value value);
88 
89  MemDirAttr inferMemoryPortKind(MemoryPortOp memPort);
90 
91  void replaceMem(Operation *op, StringRef name, bool isSequential, RUWAttr ruw,
92  ArrayAttr annotations);
93 
94  template <typename OpType, typename... T>
95  void cloneSubindexOpForMemory(OpType op, Value input, T... operands);
96 
97  void runOnOperation() override;
98 
99  /// Cached constants.
100  DenseMap<unsigned, Value> constCache;
101  DenseMap<Type, Value> invalidCache;
102 
103  /// List of operations to delete at the end of the pass.
104  SmallVector<Operation *> opsToDelete;
105 
106  /// This tracks how the result of a subfield operation which is indexes a
107  /// MemoryPortOp is used. This is used to track if the subfield operation
108  /// needs to be cloned to access a memories rdata or wdata.
109  DenseMap<Operation *, MemDirAttr> subfieldDirs;
110 
111  /// This maps a subfield-like operation from a MemoryPortOp to a new subfield
112  /// operation which can be used to read from the MemoryOp. This is used to
113  /// update any operations to read from the new memory.
114  DenseMap<Value, Value> rdataValues;
115 
116  /// This maps a subfield-like operation from a MemoryPortOp to a new subfield
117  /// operation which can be used to write to the memory, the mask value which
118  /// should be set to 1, and the corresponding wmode port of the memory which
119  /// should be set to 1. Not all memories have wmodes, so this field can
120  /// be null. This is used to update operations to write to the new memory.
121  struct WDataInfo {
122  Value data;
123  Value mask;
124  Value mode;
125  };
126  DenseMap<Value, WDataInfo> wdataValues;
127 };
128 } // end anonymous namespace
129 
130 /// Performs the callback for each leaf element of a value. This will create
131 /// any subindex and subfield operations needed to access the leaf values of the
132 /// aggregate value.
133 static void forEachLeaf(ImplicitLocOpBuilder &builder, Value value,
134  llvm::function_ref<void(Value)> func) {
135  auto type = value.getType();
136  if (auto bundleType = type_dyn_cast<BundleType>(type)) {
137  for (size_t i = 0, e = bundleType.getNumElements(); i < e; ++i)
138  forEachLeaf(builder, builder.create<SubfieldOp>(value, i), func);
139  } else if (auto vectorType = type_dyn_cast<FVectorType>(type)) {
140  for (size_t i = 0, e = vectorType.getNumElements(); i != e; ++i)
141  forEachLeaf(builder, builder.create<SubindexOp>(value, i), func);
142  } else {
143  func(value);
144  }
145 }
146 
147 /// Drive a value to all leafs of the input aggregate value. This only makes
148 /// sense when all leaf values have the same type, since the same value will be
149 /// connected to each leaf. This does not work for aggregates with flip types.
150 static void connectLeafsTo(ImplicitLocOpBuilder &builder, Value bundle,
151  Value value) {
152  forEachLeaf(builder, bundle,
153  [&](Value leaf) { emitConnect(builder, leaf, value); });
154 }
155 
156 /// Connect each leaf of an aggregate type to invalid. This does not support
157 /// aggregates with flip types.
158 void LowerCHIRRTLPass::emitInvalid(ImplicitLocOpBuilder &builder, Value value) {
159  auto type = value.getType();
160  auto &invalid = invalidCache[type];
161  if (!invalid) {
162  auto builder = OpBuilder::atBlockBegin(getOperation().getBodyBlock());
163  invalid = builder.create<InvalidValueOp>(getOperation().getLoc(), type);
164  }
165  emitConnect(builder, value, invalid);
166 }
167 
168 /// Converts a CHIRRTL memory port direction to a MemoryOp port type. The
169 /// biggest difference is that there is no match for the Infer port type.
170 static MemOp::PortKind memDirAttrToPortKind(MemDirAttr direction) {
171  switch (direction) {
172  case MemDirAttr::Read:
173  return MemOp::PortKind::Read;
174  case MemDirAttr::Write:
175  return MemOp::PortKind::Write;
176  case MemDirAttr::ReadWrite:
177  return MemOp::PortKind::ReadWrite;
178  default:
179  llvm_unreachable(
180  "Unhandled MemDirAttr, was the port direction not inferred?");
181  }
182 }
183 
184 /// This function infers the memory direction of each CHIRRTL memory port. Each
185 /// memory port has an initial memory direction which is explicitly declared in
186 /// the MemoryPortOp, which is used as a starting point. For example, if the
187 /// port is declared to be Write, but it is only ever read from, the port will
188 /// become a ReadWrite port.
189 ///
190 /// When the memory port is eventually replaced with a memory, we will go from
191 /// having a single data value to having separate rdata and wdata values. In
192 /// this function we record how the result of each data subfield operation is
193 /// used, so that later on we can make sure the SubfieldOp is cloned to index
194 /// into the correct rdata and wdata fields of the memory.
195 MemDirAttr LowerCHIRRTLPass::inferMemoryPortKind(MemoryPortOp memPort) {
196  // This function does a depth-first walk of the use-lists of the memport
197  // operation to look through subindex operations and find the places where it
198  // is ultimately used. At each node we record how the children ops are using
199  // the result of the current operation. When we are done visiting the current
200  // operation we store how it is used into a global hashtable for later use.
201  // This records how both the MemoryPort and Subfield operations are used.
202  struct StackElement {
203  StackElement(Value value, Value::use_iterator iterator, MemDirAttr mode)
204  : value(value), iterator(iterator), mode(mode) {}
205  Value value;
206  Value::use_iterator iterator;
207  MemDirAttr mode;
208  };
209 
210  SmallVector<StackElement> stack;
211  stack.emplace_back(memPort.getData(), memPort.getData().use_begin(),
212  memPort.getDirection());
213  MemDirAttr mode = MemDirAttr::Infer;
214 
215  while (!stack.empty()) {
216  auto *iter = &stack.back().iterator;
217  auto end = stack.back().value.use_end();
218  stack.back().mode |= mode;
219 
220  while (*iter != end) {
221  auto &element = stack.back();
222  auto &use = *(*iter);
223  auto *user = use.getOwner();
224  ++(*iter);
225  if (isa<SubindexOp, SubfieldOp>(user)) {
226  // We recurse into Subindex ops to find the leaf-uses.
227  auto output = user->getResult(0);
228  stack.emplace_back(output, output.use_begin(), MemDirAttr::Infer);
229  mode = MemDirAttr::Infer;
230  iter = &stack.back().iterator;
231  end = output.use_end();
232  continue;
233  }
234  if (auto subaccessOp = dyn_cast<SubaccessOp>(user)) {
235  // Subaccess has two arguments, the vector and the index. If we are
236  // using the memory port as an index, we can ignore it. If we are using
237  // the memory as the vector, we need to recurse.
238  auto input = subaccessOp.getInput();
239  if (use.get() == input) {
240  auto output = subaccessOp.getResult();
241  stack.emplace_back(output, output.use_begin(), MemDirAttr::Infer);
242  mode = MemDirAttr::Infer;
243  iter = &stack.back().iterator;
244  end = output.use_end();
245  continue;
246  }
247  // Otherwise we are reading from a memory for the index.
248  element.mode |= MemDirAttr::Read;
249  } else if (auto connectOp = dyn_cast<ConnectOp>(user)) {
250  if (use.get() == connectOp.getDest()) {
251  element.mode |= MemDirAttr::Write;
252  } else {
253  element.mode |= MemDirAttr::Read;
254  }
255  } else if (auto connectOp = dyn_cast<MatchingConnectOp>(user)) {
256  if (use.get() == connectOp.getDest()) {
257  element.mode |= MemDirAttr::Write;
258  } else {
259  element.mode |= MemDirAttr::Read;
260  }
261  } else {
262  // Every other use of a memory is a read operation.
263  element.mode |= MemDirAttr::Read;
264  }
265  }
266  mode = stack.back().mode;
267 
268  // Store the direction of the current operation in the global map. This will
269  // be used later to determine if this subaccess operation needs to be cloned
270  // into rdata, wdata, and wmask.
271  subfieldDirs[stack.back().value.getDefiningOp()] = mode;
272  stack.pop_back();
273  }
274 
275  return mode;
276 }
277 
278 void LowerCHIRRTLPass::replaceMem(Operation *cmem, StringRef name,
279  bool isSequential, RUWAttr ruw,
280  ArrayAttr annotations) {
281  assert(isa<CombMemOp>(cmem) || isa<SeqMemOp>(cmem));
282 
283  // We have several early breaks in this function, so we record the CHIRRTL
284  // memory for deletion here.
285  opsToDelete.push_back(cmem);
286  ++numLoweredMems;
287 
288  auto cmemType = type_cast<CMemoryType>(cmem->getResult(0).getType());
289  auto depth = cmemType.getNumElements();
290  auto type = cmemType.getElementType();
291 
292  // Collect the information from each of the CMemoryPorts.
293  struct PortInfo {
294  StringAttr name;
295  Type type;
296  Attribute annotations;
297  MemOp::PortKind portKind;
298  Operation *cmemPort;
299  };
300  SmallVector<PortInfo, 4> ports;
301  for (auto *user : cmem->getUsers()) {
302  MemOp::PortKind portKind;
303  StringAttr portName;
304  ArrayAttr portAnnos;
305  if (auto cmemoryPort = dyn_cast<MemoryPortOp>(user)) {
306  // Infer the type of memory port we need to create.
307  auto portDirection = inferMemoryPortKind(cmemoryPort);
308 
309  // If the memory port is never used, it will have the Infer type and
310  // should just be deleted. TODO: this is mirroring SFC, but should we be
311  // checking for annotations on the memory port before removing it?
312  if (portDirection == MemDirAttr::Infer)
313  continue;
314  portKind = memDirAttrToPortKind(portDirection);
315  portName = cmemoryPort.getNameAttr();
316  portAnnos = cmemoryPort.getAnnotationsAttr();
317  } else if (auto dPort = dyn_cast<MemoryDebugPortOp>(user)) {
318  portKind = MemOp::PortKind::Debug;
319  portName = dPort.getNameAttr();
320  portAnnos = dPort.getAnnotationsAttr();
321  } else {
322  user->emitOpError("unhandled user of chirrtl memory");
323  return;
324  }
325 
326  // Add the new port.
327  ports.push_back({portName, MemOp::getTypeForPort(depth, type, portKind),
328  portAnnos, portKind, user});
329  }
330 
331  // If there are no valid memory ports, don't create a memory.
332  if (ports.empty()) {
333  ++numPortlessMems;
334  return;
335  }
336 
337  // Canonicalize the ports into alphabetical order.
338  llvm::array_pod_sort(ports.begin(), ports.end(),
339  [](const PortInfo *lhs, const PortInfo *rhs) -> int {
340  return lhs->name.getValue().compare(
341  rhs->name.getValue());
342  });
343 
344  SmallVector<Attribute, 4> resultNames;
345  SmallVector<Type, 4> resultTypes;
346  SmallVector<Attribute, 4> portAnnotations;
347  for (auto port : ports) {
348  resultNames.push_back(port.name);
349  resultTypes.push_back(port.type);
350  portAnnotations.push_back(port.annotations);
351  }
352 
353  // Write latency is always 1, while the read latency depends on the memory
354  // type.
355  auto readLatency = isSequential ? 1 : 0;
356  auto writeLatency = 1;
357 
358  // Create the memory.
359  ImplicitLocOpBuilder memBuilder(cmem->getLoc(), cmem);
360  auto symOp = cast<hw::InnerSymbolOpInterface>(cmem);
361  auto memory = memBuilder.create<MemOp>(
362  resultTypes, readLatency, writeLatency, depth, ruw,
363  memBuilder.getArrayAttr(resultNames), name,
364  cmem->getAttrOfType<firrtl::NameKindEnumAttr>("nameKind").getValue(),
365  annotations, memBuilder.getArrayAttr(portAnnotations),
366  symOp.getInnerSymAttr(),
367  cmem->getAttrOfType<firrtl::MemoryInitAttr>("init"), StringAttr());
368  ++numCreatedMems;
369 
370  // Process each memory port, initializing the memory port and inferring when
371  // to set the enable signal high.
372  for (unsigned i = 0, e = memory.getNumResults(); i < e; ++i) {
373  auto memoryPort = memory.getResult(i);
374  auto portKind = ports[i].portKind;
375  if (portKind == MemOp::PortKind::Debug) {
376  rdataValues[ports[i].cmemPort->getResult(0)] = memoryPort;
377  continue;
378  }
379  auto cmemoryPort = cast<MemoryPortOp>(ports[i].cmemPort);
380  auto cmemoryPortAccess = cmemoryPort.getAccess();
381 
382  // Most fields on the newly created memory will be assigned an initial value
383  // immediately following the memory decl, and then will be assigned a second
384  // value at the location of the CHIRRTL memory port.
385 
386  // Initialization at the MemoryOp.
387  ImplicitLocOpBuilder portBuilder(cmemoryPortAccess.getLoc(),
388  cmemoryPortAccess);
389  auto address = memBuilder.create<SubfieldOp>(memoryPort, "addr");
390  emitInvalid(memBuilder, address);
391  auto enable = memBuilder.create<SubfieldOp>(memoryPort, "en");
392  emitConnect(memBuilder, enable, getConst(0));
393  auto clock = memBuilder.create<SubfieldOp>(memoryPort, "clk");
394  emitInvalid(memBuilder, clock);
395 
396  // Initialization at the MemoryPortOp.
397  emitConnect(portBuilder, address, cmemoryPortAccess.getIndex());
398  // Sequential+Read ports have a more complicated "enable inference".
399  auto useEnableInference = isSequential && portKind == MemOp::PortKind::Read;
400  auto *addressOp = cmemoryPortAccess.getIndex().getDefiningOp();
401  // If the address value is not something with a "name", then we do not use
402  // enable inference.
403  useEnableInference &=
404  !addressOp || isa<WireOp, NodeOp, RegOp, RegResetOp>(addressOp);
405 
406  // Most memory ports just tie their enable line to one.
407  if (!useEnableInference)
408  emitConnect(portBuilder, enable, getConst(1));
409 
410  emitConnect(portBuilder, clock, cmemoryPortAccess.getClock());
411 
412  if (portKind == MemOp::PortKind::Read) {
413  // Store the read information for updating subfield ops.
414  auto data = memBuilder.create<SubfieldOp>(memoryPort, "data");
415  rdataValues[cmemoryPort.getData()] = data;
416  } else if (portKind == MemOp::PortKind::Write) {
417  // Initialization at the MemoryOp.
418  auto data = memBuilder.create<SubfieldOp>(memoryPort, "data");
419  emitInvalid(memBuilder, data);
420  auto mask = memBuilder.create<SubfieldOp>(memoryPort, "mask");
421  emitInvalid(memBuilder, mask);
422 
423  // Initialization at the MemoryPortOp.
424  connectLeafsTo(portBuilder, mask, getConst(0));
425 
426  // Store the write information for updating subfield ops.
427  wdataValues[cmemoryPort.getData()] = {data, mask, nullptr};
428  } else if (portKind == MemOp::PortKind::ReadWrite) {
429  // Initialization at the MemoryOp.
430  auto rdata = memBuilder.create<SubfieldOp>(memoryPort, "rdata");
431  auto wmode = memBuilder.create<SubfieldOp>(memoryPort, "wmode");
432  emitConnect(memBuilder, wmode, getConst(0));
433  auto wdata = memBuilder.create<SubfieldOp>(memoryPort, "wdata");
434  emitInvalid(memBuilder, wdata);
435  auto wmask = memBuilder.create<SubfieldOp>(memoryPort, "wmask");
436  emitInvalid(memBuilder, wmask);
437 
438  // Initialization at the MemoryPortOp.
439  connectLeafsTo(portBuilder, wmask, getConst(0));
440 
441  // Store the read and write information for updating subfield ops.
442  wdataValues[cmemoryPort.getData()] = {wdata, wmask, wmode};
443  rdataValues[cmemoryPort.getData()] = rdata;
444  }
445 
446  // Sequential read only memory ports have "enable inference", which
447  // detects when to set the enable high. All other memory ports set the
448  // enable high when the memport is declared. This is higly questionable
449  // logic that is easily defeated. This behaviour depends on the kind of
450  // operation used as the memport index.
451  if (useEnableInference) {
452  auto *indexOp = cmemoryPortAccess.getIndex().getDefiningOp();
453  bool success = false;
454  if (!indexOp) {
455  // TODO: SFC does not infer any enable when using a module port as the
456  // address. This seems like something that should be fixed sooner
457  // rather than later.
458  } else if (isa<WireOp, RegResetOp, RegOp>(indexOp)) {
459  // If the address is a reference, then we set the enable whenever the
460  // address is driven.
461 
462  // Find the uses of the address that write a value to it, ignoring the
463  // ones driving an invalid value.
464  auto drivers =
465  make_filter_range(indexOp->getUsers(), [&](Operation *op) {
466  if (auto connectOp = dyn_cast<ConnectOp>(op)) {
467  if (cmemoryPortAccess.getIndex() == connectOp.getDest())
468  return !dyn_cast_or_null<InvalidValueOp>(
469  connectOp.getSrc().getDefiningOp());
470  } else if (auto connectOp = dyn_cast<MatchingConnectOp>(op)) {
471  if (cmemoryPortAccess.getIndex() == connectOp.getDest())
472  return !dyn_cast_or_null<InvalidValueOp>(
473  connectOp.getSrc().getDefiningOp());
474  }
475  return false;
476  });
477 
478  // At each location where we drive a value to the index, set the enable.
479  for (auto *driver : drivers) {
480  ImplicitLocOpBuilder builder(driver->getLoc(), driver);
481  emitConnect(builder, enable, getConst(1));
482  success = true;
483  }
484  } else if (isa<NodeOp>(indexOp)) {
485  // If using a Node for the address, then the we place the enable at the
486  // Node op's
487  ImplicitLocOpBuilder builder(indexOp->getLoc(), indexOp);
488  emitConnect(builder, enable, getConst(1));
489  success = true;
490  }
491 
492  // If we don't infer any enable points, it is almost always a user error.
493  if (!success)
494  cmemoryPort.emitWarning("memory port is never enabled");
495  }
496  }
497 }
498 
499 void LowerCHIRRTLPass::visitCHIRRTL(CombMemOp combmem) {
500  replaceMem(combmem, combmem.getName(), /*isSequential*/ false,
501  RUWAttr::Undefined, combmem.getAnnotations());
502 }
503 
504 void LowerCHIRRTLPass::visitCHIRRTL(SeqMemOp seqmem) {
505  replaceMem(seqmem, seqmem.getName(), /*isSequential*/ true, seqmem.getRuw(),
506  seqmem.getAnnotations());
507 }
508 
509 void LowerCHIRRTLPass::visitCHIRRTL(MemoryPortOp memPort) {
510  // The memory port is mostly handled while processing the memory.
511  opsToDelete.push_back(memPort);
512 }
513 
514 void LowerCHIRRTLPass::visitCHIRRTL(MemoryDebugPortOp memPort) {
515  // The memory port is mostly handled while processing the memory.
516  opsToDelete.push_back(memPort);
517 }
518 
519 void LowerCHIRRTLPass::visitCHIRRTL(MemoryPortAccessOp memPortAccess) {
520  // The memory port access is mostly handled while processing the memory.
521  opsToDelete.push_back(memPortAccess);
522 }
523 
524 void LowerCHIRRTLPass::visitStmt(ConnectOp connect) {
525  // Check if we are writing to a memory and, if we are, replace the
526  // destination.
527  auto writeIt = wdataValues.find(connect.getDest());
528  if (writeIt != wdataValues.end()) {
529  auto writeData = writeIt->second;
530  connect.getDestMutable().assign(writeData.data);
531  // Assign the write mask.
532  ImplicitLocOpBuilder builder(connect.getLoc(), connect);
533  connectLeafsTo(builder, writeData.mask, getConst(1));
534  // Only ReadWrite memories have a write mode.
535  if (writeData.mode)
536  emitConnect(builder, writeData.mode, getConst(1));
537  }
538  // Check if we are reading from a memory and, if we are, replace the
539  // source.
540  auto readIt = rdataValues.find(connect.getSrc());
541  if (readIt != rdataValues.end()) {
542  auto newSource = readIt->second;
543  connect.getSrcMutable().assign(newSource);
544  }
545 }
546 
547 void LowerCHIRRTLPass::visitStmt(MatchingConnectOp connect) {
548  // Check if we are writing to a memory and, if we are, replace the
549  // destination.
550  auto writeIt = wdataValues.find(connect.getDest());
551  if (writeIt != wdataValues.end()) {
552  auto writeData = writeIt->second;
553  connect.getDestMutable().assign(writeData.data);
554  // Assign the write mask.
555  ImplicitLocOpBuilder builder(connect.getLoc(), connect);
556  connectLeafsTo(builder, writeData.mask, getConst(1));
557  // Only ReadWrite memories have a write mode.
558  if (writeData.mode)
559  emitConnect(builder, writeData.mode, getConst(1));
560  }
561  // Check if we are reading from a memory and, if we are, replace the
562  // source.
563  auto readIt = rdataValues.find(connect.getSrc());
564  if (readIt != rdataValues.end()) {
565  auto newSource = readIt->second;
566  connect.getSrcMutable().assign(newSource);
567  }
568 }
569 
570 /// This function will create clones of subaccess, subindex, and subfield
571 /// operations which are indexing a CHIRRTL memory ports that will index into
572 /// the new memory's data field. If a subfield result is used to read from a
573 /// memory port, it will be cloned to read from the memory's rdata field. If
574 /// the subfield is used to write to a memory port, it will be cloned twice to
575 /// write to both the wdata and wmask fields. Users of this subfield operation
576 /// will be redirected to the appropriate clone when they are visited.
577 template <typename OpType, typename... T>
578 void LowerCHIRRTLPass::cloneSubindexOpForMemory(OpType op, Value input,
579  T... operands) {
580  // If the subaccess operation has no direction recorded, then it does not
581  // index a CHIRRTL memory and will be left alone.
582  auto it = subfieldDirs.find(op);
583  if (it == subfieldDirs.end()) {
584  // The subaccess operation input could be a debug port of a CHIRRTL memory.
585  // If it exists in the map, create the replacement operation for it.
586  auto iter = rdataValues.find(input);
587  if (iter != rdataValues.end()) {
588  opsToDelete.push_back(op);
589  ImplicitLocOpBuilder builder(op->getLoc(), op);
590  rdataValues[op] = builder.create<OpType>(rdataValues[input], operands...);
591  }
592  return;
593  }
594 
595  // All uses of this op will be updated to use the appropriate clone. If the
596  // recorded direction of this subfield is Infer, then the value is not
597  // actually used to read or write from a memory port, and it will be just
598  // removed.
599  opsToDelete.push_back(op);
600 
601  auto direction = it->second;
602  ImplicitLocOpBuilder builder(op->getLoc(), op);
603 
604  // If the subaccess operation is used to read from a memory port, we need to
605  // clone it to read from the rdata field.
606  if (direction == MemDirAttr::Read || direction == MemDirAttr::ReadWrite) {
607  rdataValues[op] = builder.create<OpType>(rdataValues[input], operands...);
608  }
609 
610  // If the subaccess operation is used to write to the memory, we need to clone
611  // it to write to the wdata and the wmask fields.
612  if (direction == MemDirAttr::Write || direction == MemDirAttr::ReadWrite) {
613  auto writeData = wdataValues[input];
614  auto write = builder.create<OpType>(writeData.data, operands...);
615  auto mask = builder.create<OpType>(writeData.mask, operands...);
616  wdataValues[op] = {write, mask, writeData.mode};
617  }
618 }
619 
620 void LowerCHIRRTLPass::visitExpr(SubaccessOp subaccess) {
621  // Check if the subaccess reads from a memory for
622  // the index.
623  auto readIt = rdataValues.find(subaccess.getIndex());
624  if (readIt != rdataValues.end()) {
625  subaccess.getIndexMutable().assign(readIt->second);
626  }
627  // Handle it like normal.
628  cloneSubindexOpForMemory(subaccess, subaccess.getInput(),
629  subaccess.getIndex());
630 }
631 
632 void LowerCHIRRTLPass::visitExpr(SubfieldOp subfield) {
633  cloneSubindexOpForMemory<SubfieldOp>(subfield, subfield.getInput(),
634  subfield.getFieldIndex());
635 }
636 
637 void LowerCHIRRTLPass::visitExpr(SubindexOp subindex) {
638  cloneSubindexOpForMemory<SubindexOp>(subindex, subindex.getInput(),
639  subindex.getIndex());
640 }
641 
642 void LowerCHIRRTLPass::visitUnhandledOp(Operation *op) {
643  // For every operand, check if it is reading from a memory port and
644  // replace it with a read from the new memory.
645  for (auto &operand : op->getOpOperands()) {
646  auto it = rdataValues.find(operand.get());
647  if (it != rdataValues.end()) {
648  operand.set(it->second);
649  }
650  }
651 }
652 
653 void LowerCHIRRTLPass::runOnOperation() {
654  // Walk the entire body of the module and dispatch the visitor on each
655  // function. This will replace all CHIRRTL memories and ports, and update all
656  // uses.
657  getOperation().getBodyBlock()->walk(
658  [&](Operation *op) { dispatchCHIRRTLVisitor(op); });
659 
660  // If there are no operations to delete, then we didn't find any CHIRRTL
661  // memories.
662  if (opsToDelete.empty())
663  markAllAnalysesPreserved();
664 
665  // Remove the old memories and their ports.
666  while (!opsToDelete.empty())
667  opsToDelete.pop_back_val()->erase();
668 
669  // Clear out any cached data.
670  clear();
671 }
672 
673 std::unique_ptr<mlir::Pass> circt::firrtl::createLowerCHIRRTLPass() {
674  return std::make_unique<LowerCHIRRTLPass>();
675 }
assert(baseType &&"element must be base type")
static MemOp::PortKind memDirAttrToPortKind(MemDirAttr direction)
Converts a CHIRRTL memory port direction to a MemoryOp port type.
static void connectLeafsTo(ImplicitLocOpBuilder &builder, Value bundle, Value value)
Drive a value to all leafs of the input aggregate value.
static void forEachLeaf(ImplicitLocOpBuilder &builder, Value value, llvm::function_ref< void(Value)> func)
Performs the callback for each leaf element of a value.
static Block * getBodyBlock(FModuleLike mod)
CHIRRTLVisitor is a visitor for CHIRRTL operations.
FIRRTLVisitor allows you to visit all of the expr/stmt/decls with one class declaration.
def connect(destination, source)
Definition: support.py:39
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
Definition: CalyxOps.cpp:55
std::unique_ptr< mlir::Pass > createLowerCHIRRTLPass()
void emitConnect(OpBuilder &builder, Location loc, Value lhs, Value rhs)
Emit a connect between two values.
Definition: FIRRTLUtils.cpp:25
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
Definition: DebugAnalysis.h:21
This holds the name and type that describes the module's ports.