CIRCT  18.0.0git
Classes | Functions
circt::ExportVerilog Namespace Reference

Classes

struct  GlobalNameTable
 This class keeps track of global names at the module/interface level. More...
 
struct  NameCollisionResolver
 
struct  FieldNameResolver
 
struct  OpFileInfo
 Information to control the emission of a single operation into a file. More...
 
struct  FileInfo
 Information to control the emission of a list of operations into a file. More...
 
class  OpLocMap
 Track the output verilog line,column number information for every op. More...
 
class  StringOrOpToEmit
 This class wraps an operation or a fixed string that should be emitted. More...
 
struct  SharedEmitterState
 This class tracks the top-level state for the emitters, which is built and then shared across all per-file emissions that happen in parallel. More...
 
class  GlobalNameResolver
 This class keeps track of modules and interfaces that need to be renamed, as well as module ports, parameters, declarations and verif labels that need to be renamed. More...
 

Functions

bool isSimpleReadOrPort (Value v)
 Check if the value is from read of a wire or reg or is a port. More...
 
StringAttr inferStructuralNameForTemporary (Value expr)
 Given an expression that is spilled into a temporary wire, try to synthesize a better name than "_T_42" based on the structure of the expression. More...
 
static bool isExpressionAlwaysInline (Operation *op)
 Return true for operations that must always be inlined into a containing expression for correctness. More...
 
StringRef getSymOpName (Operation *symOp)
 Return the verilog name of the operations that can define a symbol. More...
 
static bool isConstantExpression (Operation *op)
 Return whether an operation is a constant. More...
 
bool isVerilogExpression (Operation *op)
 This predicate returns true if the specified operation is considered a potentially inlinable Verilog expression. More...
 
bool isZeroBitType (Type type)
 Return true if this is a zero bit type, e.g. More...
 
bool isExpressionEmittedInline (Operation *op, const LoweringOptions &options)
 Return true if this expression should be emitted inline into any statement that uses it. More...
 
LogicalResult prepareHWModule (Block &block, const LoweringOptions &options)
 For each module we emit, do a prepass over the structure, pre-lowering and otherwise rewriting operations we don't want to emit. More...
 
LogicalResult prepareHWModule (hw::HWModuleOp module, const LoweringOptions &options)
 
void pruneZeroValuedLogic (hw::HWModuleOp module)
 
GlobalNameTable legalizeGlobalNames (ModuleOp topLevel, const LoweringOptions &options)
 Rewrite module names and interfaces to not conflict with each other or with Verilog keywords. More...
 

Function Documentation

◆ getSymOpName()

StringRef circt::ExportVerilog::getSymOpName ( Operation *  symOp)

Return the verilog name of the operations that can define a symbol.

Legalized names are added to "hw.verilogName" so look up it when the attribute already exists.

Definition at line 185 of file ExportVerilog.cpp.

References circt::hw::getVerilogModuleName(), and circt::hw::getVerilogModuleNameAttr().

Referenced by getVerilogValueName(), inferStructuralNameForTemporary(), and legalizeModuleLocalNames().

◆ inferStructuralNameForTemporary()

StringAttr circt::ExportVerilog::inferStructuralNameForTemporary ( Value  expr)

Given an expression that is spilled into a temporary wire, try to synthesize a better name than "_T_42" based on the structure of the expression.

Definition at line 1365 of file ExportVerilog.cpp.

References circt::calyx::direction::get(), getPortVerilogName(), and getSymOpName().

Referenced by lowerUsersToTemporaryWire().

◆ isConstantExpression()

static bool circt::ExportVerilog::isConstantExpression ( Operation *  op)
inlinestatic

Return whether an operation is a constant.

Definition at line 410 of file ExportVerilogInternals.h.

Referenced by isDuplicatableNullaryExpression(), and legalizeHWModule().

◆ isExpressionAlwaysInline()

static bool circt::ExportVerilog::isExpressionAlwaysInline ( Operation *  op)
inlinestatic

Return true for operations that must always be inlined into a containing expression for correctness.

Definition at line 386 of file ExportVerilogInternals.h.

Referenced by hoistNonSideEffectExpr(), legalizeHWModule(), lowerAlwaysInlineOperation(), and reuseExistingInOut().

◆ isExpressionEmittedInline()

bool circt::ExportVerilog::isExpressionEmittedInline ( Operation *  op,
const LoweringOptions options 
)

Return true if this expression should be emitted inline into any statement that uses it.

Definition at line 887 of file ExportVerilog.cpp.

References circt::LoweringOptions::disallowMuxInlining, isDuplicatableExpression(), and isExpressionUnableToInline().

Referenced by isExpressionEmittedInlineIntoProceduralDeclaration(), and shouldSpillWire().

◆ isSimpleReadOrPort()

bool circt::ExportVerilog::isSimpleReadOrPort ( Value  v)

Check if the value is from read of a wire or reg or is a port.

Definition at line 42 of file PrepareForEmission.cpp.

Referenced by spillWiresForInstanceInputs().

◆ isVerilogExpression()

bool circt::ExportVerilog::isVerilogExpression ( Operation *  op)

This predicate returns true if the specified operation is considered a potentially inlinable Verilog expression.

These nodes always have a single result, but may have side effects (e.g. sv.verbatim.expr.se). MemoryEffects should be checked if a client cares.

Definition at line 247 of file ExportVerilog.cpp.

References isCombinational(), and circt::firrtl::isExpression().

Referenced by countStatements(), findNestedElseIf(), isExpressionEmittedInlineIntoProceduralDeclaration(), legalizeHWModule(), prettifyAfterLegalization(), and shouldSpillWire().

◆ isZeroBitType()

bool circt::ExportVerilog::isZeroBitType ( Type  type)

Return true if this is a zero bit type, e.g.

a zero bit integer or array thereof.

Definition at line 303 of file ExportVerilog.cpp.

References circt::hw::getBitWidth(), and circt::hw::getCanonicalType().

Referenced by lowerInstanceResults(), and noI0Type().

◆ legalizeGlobalNames()

GlobalNameTable circt::ExportVerilog::legalizeGlobalNames ( ModuleOp  topLevel,
const LoweringOptions options 
)

Rewrite module names and interfaces to not conflict with each other or with Verilog keywords.

Definition at line 333 of file LegalizeNames.cpp.

References circt::ExportVerilog::GlobalNameResolver::takeGlobalNameTable().

Referenced by exportSplitVerilogImpl(), and exportVerilogImpl().

◆ prepareHWModule() [1/2]

LogicalResult circt::ExportVerilog::prepareHWModule ( Block &  block,
const LoweringOptions options 
)

For each module we emit, do a prepass over the structure, pre-lowering and otherwise rewriting operations we don't want to emit.

◆ prepareHWModule() [2/2]

LogicalResult circt::ExportVerilog::prepareHWModule ( hw::HWModuleOp  module,
const LoweringOptions options 
)

◆ pruneZeroValuedLogic()

void circt::ExportVerilog::pruneZeroValuedLogic ( hw::HWModuleOp  module)

Definition at line 244 of file PruneZeroValuedLogic.cpp.

Referenced by prepareHWModule().