Classes
struct	GlobalNameTable
	This class keeps track of global names at the module/interface level. More...
struct	NameCollisionResolver
struct	FieldNameResolver
struct	OpFileInfo
	Information to control the emission of a single operation into a file. More...
struct	FileInfo
	Information to control the emission of a list of operations into a file. More...
class	OpLocMap
	Track the output verilog line,column number information for every op. More...
class	StringOrOpToEmit
	This class wraps an operation or a fixed string that should be emitted. More...
struct	SharedEmitterState
	This class tracks the top-level state for the emitters, which is built and then shared across all per-file emissions that happen in parallel. More...
class	GlobalNameResolver
	This class keeps track of modules and interfaces that need to be renamed, as well as module ports, parameters, declarations and verif labels that need to be renamed. More...

Typedefs
using	FileMapping = DenseMap<StringAttr, Operation *>
	Mapping from symbols to file operations.
using	FragmentMapping = DenseMap<StringAttr, emit::FragmentOp>
	Mapping from symbols to file operations.

Functions
bool	isSimpleReadOrPort (Value v)
	Check if the value is from read of a wire or reg or is a port.
StringAttr	inferStructuralNameForTemporary (Value expr)
	Given an expression that is spilled into a temporary wire, try to synthesize a better name than "_T_42" based on the structure of the expression.
static bool	isExpressionAlwaysInline (Operation *op)
	Return true for operations that must always be inlined into a containing expression for correctness.
StringRef	getSymOpName (Operation *symOp)
	Return the verilog name of the operations that can define a symbol.
static bool	isConstantExpression (Operation *op)
	Return whether an operation is a constant.
bool	isVerilogExpression (Operation *op)
	This predicate returns true if the specified operation is considered a potentially inlinable Verilog expression.
bool	isZeroBitType (Type type)
	Return true if this is a zero bit type, e.g.
bool	isExpressionEmittedInline (Operation *op, const LoweringOptions &options)
	Return true if this expression should be emitted inline into any statement that uses it.
LogicalResult	lowerHWInstanceChoices (mlir::ModuleOp module)
	Generates the macros used by instance choices.
LogicalResult	prepareHWModule (Block &block, const LoweringOptions &options)
	For each module we emit, do a prepass over the structure, pre-lowering and otherwise rewriting operations we don't want to emit.
LogicalResult	prepareHWModule (hw::HWEmittableModuleLike module, const LoweringOptions &options)
void	pruneZeroValuedLogic (hw::HWEmittableModuleLike module)
GlobalNameTable	legalizeGlobalNames (ModuleOp topLevel, const LoweringOptions &options)
	Rewrite module names and interfaces to not conflict with each other or with Verilog keywords.

Typedef Documentation

◆ FileMapping

using circt::ExportVerilog::FileMapping = DenseMap<StringAttr, Operation *>

Mapping from symbols to file operations.

Definition at line 347 of file ExportVerilogInternals.h.

◆ FragmentMapping

using circt::ExportVerilog::FragmentMapping = DenseMap<StringAttr, emit::FragmentOp>

Mapping from symbols to file operations.

Definition at line 350 of file ExportVerilogInternals.h.

Function Documentation

◆ getSymOpName()

StringRef circt::ExportVerilog::getSymOpName ( Operation * symOp )

Return the verilog name of the operations that can define a symbol.

Legalized names are added to "hw.verilogName" so look up it when the attribute already exists.

Definition at line 193 of file ExportVerilog.cpp.

References circt::hw::getVerilogModuleName(), and circt::hw::getVerilogModuleNameAttr().

Referenced by emitFunctionSignature(), circt::ExportVerilog::SharedEmitterState::gatherFiles(), circt::ExportVerilog::FieldNameResolver::getEnumFieldName(), getVerilogValueName(), inferStructuralNameForTemporary(), legalizeModuleLocalNames(), and circt::ExportVerilog::GlobalNameResolver::legalizePackageNames().

◆ inferStructuralNameForTemporary()

StringAttr circt::ExportVerilog::inferStructuralNameForTemporary ( Value expr )

Given an expression that is spilled into a temporary wire, try to synthesize a better name than "_T_42" based on the structure of the expression.

Definition at line 1393 of file ExportVerilog.cpp.

References getPortVerilogName(), getSymOpName(), and inferStructuralNameForTemporary().

Referenced by inferStructuralNameForTemporary(), and lowerUsersToTemporaryWire().

◆ isConstantExpression()

bool circt::ExportVerilog::isConstantExpression ( Operation * op )

inlinestatic

Return whether an operation is a constant.

Definition at line 440 of file ExportVerilogInternals.h.

Referenced by isDuplicatableNullaryExpression(), and legalizeHWModule().

◆ isExpressionAlwaysInline()

bool circt::ExportVerilog::isExpressionAlwaysInline ( Operation * op )

inlinestatic

Return true for operations that must always be inlined into a containing expression for correctness.

Definition at line 416 of file ExportVerilogInternals.h.

Referenced by hoistNonSideEffectExpr(), legalizeHWModule(), lowerAlwaysInlineOperation(), and reuseExistingInOut().

◆ isExpressionEmittedInline()

bool circt::ExportVerilog::isExpressionEmittedInline	(	Operation *	op,
		const LoweringOptions &	options )

Return true if this expression should be emitted inline into any statement that uses it.

Definition at line 895 of file ExportVerilog.cpp.

References circt::LoweringOptions::disallowMuxInlining, isDuplicatableExpression(), and isExpressionUnableToInline().

Referenced by isExpressionEmittedInlineIntoProceduralDeclaration(), and shouldSpillWire().

◆ isSimpleReadOrPort()

bool circt::ExportVerilog::isSimpleReadOrPort ( Value v )

Check if the value is from read of a wire or reg or is a port.

Definition at line 52 of file PrepareForEmission.cpp.

Referenced by spillWiresForInstanceInputs().

◆ isVerilogExpression()

bool circt::ExportVerilog::isVerilogExpression ( Operation * op )

This predicate returns true if the specified operation is considered a potentially inlinable Verilog expression.

These nodes always have a single result, but may have side effects (e.g. sv.verbatim.expr.se). MemoryEffects should be checked if a client cares.

Definition at line 255 of file ExportVerilog.cpp.

References circt::hw::isCombinational().

Referenced by countStatements(), findNestedElseIf(), isExpressionEmittedInlineIntoProceduralDeclaration(), legalizeHWModule(), prettifyAfterLegalization(), and shouldSpillWire().

◆ isZeroBitType()

bool circt::ExportVerilog::isZeroBitType ( Type type )

Return true if this is a zero bit type, e.g.

a zero bit integer or array thereof.

Definition at line 325 of file ExportVerilog.cpp.

References circt::hw::getCanonicalType(), and isZeroBitType().

Referenced by isZeroBitType(), lowerInstanceResults(), and noI0Type().

◆ legalizeGlobalNames()

GlobalNameTable circt::ExportVerilog::legalizeGlobalNames	(	ModuleOp	topLevel,
		const LoweringOptions &	options )

Rewrite module names and interfaces to not conflict with each other or with Verilog keywords.

Definition at line 437 of file LegalizeNames.cpp.

References circt::ExportVerilog::GlobalNameResolver::takeGlobalNameTable().

Referenced by exportSplitVerilogImpl(), and exportVerilogImpl().

◆ lowerHWInstanceChoices()

LogicalResult circt::ExportVerilog::lowerHWInstanceChoices ( mlir::ModuleOp module )

Generates the macros used by instance choices.

◆ prepareHWModule() [1/2]

LogicalResult circt::ExportVerilog::prepareHWModule	(	Block &	block,
		const LoweringOptions &	options )

For each module we emit, do a prepass over the structure, pre-lowering and otherwise rewriting operations we don't want to emit.

◆ prepareHWModule() [2/2]

LogicalResult circt::ExportVerilog::prepareHWModule	(	hw::HWEmittableModuleLike	module,
		const LoweringOptions &	options )

Definition at line 1387 of file PrepareForEmission.cpp.

References failure(), circt::LoweringOptions::fixUpEmptyModules, fixUpEmptyModules(), legalizeHWModule(), prettifyAfterLegalization(), pruneZeroValuedLogic(), and success().

◆ pruneZeroValuedLogic()

void circt::ExportVerilog::pruneZeroValuedLogic ( hw::HWEmittableModuleLike module )

Referenced by prepareHWModule().

Classes

Typedefs

Functions