150 if (
auto hwModule = dyn_cast<hw::HWModuleOp>(*module))
151 for (
auto param : hwModule.getParameters())
153 module, cast<ParamDeclAttr>(param).getName()));
155 auto *ctxt =
module.getContext();
157 auto verilogNameAttr = StringAttr::get(ctxt,
"hw.verilogName");
159 auto ports =
module.getPortList();
160 SmallVector<Attribute> newNames(ports.size());
161 bool updated =
false;
162 bool isFuncOp = isa<FuncOp>(module);
163 for (
auto [idx, port] : llvm::enumerate(ports)) {
164 auto verilogName = port.attrs.get(verilogNameAttr);
167 if (isFuncOp && port.attrs.get(FuncOp::getExplicitlyReturnedAttrName())) {
169 newNames[idx] = StringAttr::get(ctxt,
getSymOpName(module));
173 auto newName = StringAttr::get(
174 ctxt, nameResolver.
getLegalName(cast<StringAttr>(verilogName)));
175 newNames[idx] = newName;
176 if (verilogName != newName)
180 auto oldName = ports[idx].name;
183 if (newName != oldName) {
184 newNames[idx] = StringAttr::get(ctxt, newName);
190 module.setPortAttrs(verilogNameAttr, newNames);
192 SmallVector<std::pair<Operation *, StringAttr>> nameEntries;
195 module.walk([&](Operation *op) {
198 if (auto name = op->getAttrOfType<StringAttr>(verilogNameAttr)) {
199 nameResolver.insertUsedName(
200 op->getAttrOfType<StringAttr>(verilogNameAttr));
202 hw::InstanceOp, sv::InterfaceInstanceOp, sv::GenerateOp>(
205 nameEntries.emplace_back(
206 op, StringAttr::get(op->getContext(),
getSymOpName(op)));
207 }
else if (
auto forOp = dyn_cast<ForOp>(op)) {
208 nameEntries.emplace_back(op, forOp.getInductionVarNameAttr());
209 }
else if (isa<AssertOp, AssumeOp, CoverOp, AssertConcurrentOp,
210 AssumeConcurrentOp, CoverConcurrentOp, AssertPropertyOp,
211 AssumePropertyOp, CoverPropertyOp, verif::AssertOp,
212 verif::CoverOp, verif::AssumeOp>(op)) {
214 if (
auto labelAttr = op->getAttrOfType<StringAttr>(
"label"))
215 nameEntries.emplace_back(op, labelAttr);
216 else if (options.enforceVerifLabels) {
219 StringRef defaultName =
220 llvm::TypeSwitch<Operation *, StringRef>(op)
221 .Case<AssertOp, AssertConcurrentOp, AssertPropertyOp,
222 verif::AssertOp>([](
auto) {
return "assert"; })
223 .Case<CoverOp, CoverConcurrentOp, CoverPropertyOp,
224 verif::CoverOp>([](
auto) {
return "cover"; })
225 .Case<AssumeOp, AssumeConcurrentOp, AssumePropertyOp,
226 verif::AssumeOp>([](
auto) {
return "assume"; });
227 nameEntries.emplace_back(
228 op, StringAttr::get(op->getContext(), defaultName));
234 for (
auto [op, nameAttr] : nameEntries) {
235 auto newName = nameResolver.getLegalName(nameAttr);
236 assert(!newName.empty() &&
"must have a valid name");
238 op->setAttr(verilogNameAttr, nameAttr.getValue() == newName
240 : StringAttr::
get(
ctxt, newName));
248 : globalNameResolver(options), options(options) {
253 for (
auto &op : *topLevel.getBody()) {
256 if (isa<HWModuleExternOp>(op) || isa<HWModuleGeneratedOp>(op)) {
259 op.emitError(
"name \"")
260 << name <<
"\" is not allowed in Verilog output";
262 }
else if (
auto reservedNamesOp = dyn_cast<sv::ReserveNamesOp>(op)) {
263 for (StringAttr name :
264 reservedNamesOp.getReservedNames().getAsRange<StringAttr>()) {
272 for (
auto &op : *topLevel.getBody()) {
273 if (
auto module = dyn_cast<HWModuleOp>(op)) {
280 if (
auto interface = dyn_cast<InterfaceOp>(op)) {
287 mlir::parallelForEach(
288 topLevel.getContext(), topLevel.getOps<HWEmittableModuleLike>(),
290 legalizeModuleLocalNames(module, options, globalNameTable);
337 MLIRContext *ctxt = interface.getContext();
338 auto verilogNameAttr = StringAttr::get(ctxt,
"hw.verilogName");
340 if (newName != interface.getName())
341 interface->setAttr(verilogNameAttr, StringAttr::get(ctxt, newName));
345 for (
auto &op : *interface.getBodyBlock()) {
346 if (isa<InterfaceSignalOp, InterfaceModportOp>(op)) {
347 auto name = SymbolTable::getSymbolName(&op).getValue();
350 op.setAttr(verilogNameAttr, StringAttr::get(ctxt, newName));