'chirrtl' Dialect

Types and operations for the chirrtl dialect

This dialect defines the chirrtl dialect, which contains high-level memory defintions which can be lowered to FIRRTL.

Operations ¶

chirrtl.combmem (::circt::chirrtl::CombMemOp) ¶

Define a new combinational memory

Syntax:

operation ::= `chirrtl.combmem` (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
              `` custom<CombMemOp>(attr-dict) `:` qualified(type($result))

Define a new behavioral combinational memory. Combinational memories have a write latency of 1 and a read latency of 0.

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbolOpInterface

Attributes: ¶

Results: ¶

chirrtl.debugport (::circt::chirrtl::MemoryDebugPortOp) ¶

Defines a debug memory port on CHIRRTL memory

Syntax:

operation ::= `chirrtl.debugport` $memory custom<MemoryDebugPortOp>(attr-dict) `:`
              functional-type(operands, results)

This operation defines a new debug memory port on a combmemCHISEL. data is the data returned from the memory port.

Interfaces: HasCustomSSAName, InferTypeOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

chirrtl.memoryport (::circt::chirrtl::MemoryPortOp) ¶

Defines a memory port on CHIRRTL memory

Syntax:

operation ::= `chirrtl.memoryport` $direction $memory `` custom<MemoryPortOp>(attr-dict) `:`
              functional-type(operands, results)

This operation defines a new memory port on a seqmem or combmemCHISEL. data is the data returned from the memory port.

The memory port requires an access point, which sets the enable condition of the port, the clock, and the address. This is done by passing the the port argument to a chirrtl.memoryport.access operation.

Interfaces: HasCustomSSAName, InferTypeOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

chirrtl.memoryport.access (::circt::chirrtl::MemoryPortAccessOp) ¶

Enables a memory port

Syntax:

operation ::= `chirrtl.memoryport.access` $port `[` $index `]` `,` $clock attr-dict `:` qualified(type(operands))

This operation is used to conditionally enable a memory port, and associate it with a clock and index. The memory port will be actuve on the positive edge of the clock. The index is the address of the memory accessed. See the FIRRTL rational for more information about why this operation exists.

Operands: ¶

chirrtl.seqmem (::circt::chirrtl::SeqMemOp) ¶

Define a new sequential memory

Syntax:

operation ::= `chirrtl.seqmem` (`sym` $inner_sym^)? `` custom<NameKind>($nameKind) $ruw
              custom<SeqMemOp>(attr-dict) `:` qualified(type($result))

Define a new behavioral sequential memory. Sequential memories have a write latency and a read latency of 1.

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbolOpInterface

Attributes: ¶

Results: ¶

Types ¶

CMemoryPortType ¶

a behavioral memory port

Syntax: !chirrtl.cmemoryport

Syntax:

cmemoryport-type ::= `cmemoryport`

The value of a cmemoryport type represents a port which has been declared on a cmemory. This value is used to set the memory port access conditions.

CMemoryType ¶

a behavioral memory

Syntax:

cmemory-type ::= `cmemory` `<` element-type, element-count `>`

The value of a cmemory type represents a behavioral memory with unknown ports. This is produced by combmem and seqmem declarations and used by memoryport declarations to define memories and their ports. A CMemory is similar to a vector of passive element types.

Examples:

!chirrtl.cmemory<uint<32>, 16>
!chirrtl.cmemory<bundle<a : uint<1>>, 16>

Parameters: ¶

Enums ¶

Convention ¶

lowering convention

Cases: ¶

EventControl ¶

edge control trigger

Cases: ¶

LayerConvention ¶

layer convention

Cases: ¶

LayerSpecialization ¶

layer specialization

Cases: ¶

MemDirAttr ¶

Memory Direction Enum

Cases: ¶

NameKindEnum ¶

name kind

Cases: ¶

RUWAttr ¶

Read Under Write Enum

Cases: ¶

TargetKind ¶

object model target kind

Cases: ¶