CIRCT  19.0.0git
Firtool.cpp
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1 //===- Firtool.cpp - Definitions for the firtool pipeline setup -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
17 #include "circt/Support/Passes.h"
19 #include "mlir/Transforms/Passes.h"
20 #include "llvm/Support/FileSystem.h"
21 #include "llvm/Support/Path.h"
22 
23 using namespace llvm;
24 using namespace circt;
25 
26 LogicalResult firtool::populatePreprocessTransforms(mlir::PassManager &pm,
27  const FirtoolOptions &opt) {
28  // Legalize away "open" aggregates to hw-only versions.
29  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerOpenAggsPass());
30 
31  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createResolvePathsPass());
32 
33  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerFIRRTLAnnotationsPass(
37 
38  if (opt.shouldEnableDebugInfo())
39  pm.nest<firrtl::CircuitOp>().addNestedPass<firrtl::FModuleOp>(
41 
42  return success();
43 }
44 
45 LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
46  const FirtoolOptions &opt,
47  StringRef inputFilename) {
48  pm.nest<firrtl::CircuitOp>().addPass(
50 
51  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerSignaturesPass());
52 
53  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInjectDUTHierarchyPass());
54 
55  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
57 
58  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
60 
61  if (!opt.shouldDisableOptimization())
62  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
63  mlir::createCSEPass());
64 
65  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
67 
68  // Run LowerMatches before InferWidths, as the latter does not support the
69  // match statement, but it does support what they lower to.
70  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
72 
73  // Width inference creates canonicalization opportunities.
74  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferWidthsPass());
75 
76  pm.nest<firrtl::CircuitOp>().addPass(
79 
80  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferResetsPass());
81 
82  if (opt.shouldExportChiselInterface()) {
83  StringRef outdir = opt.getChiselInterfaceOutputDirectory();
84  if (opt.isDefaultOutputFilename() && outdir.empty()) {
85  pm.nest<firrtl::CircuitOp>().addPass(createExportChiselInterfacePass());
86  } else {
87  if (outdir.empty())
88  outdir = opt.getOutputFilename();
89  pm.nest<firrtl::CircuitOp>().addPass(
91  }
92  }
93 
94  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDropConstPass());
95 
96  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createHoistPassthroughPass(
97  /*hoistHWDrivers=*/!opt.shouldDisableOptimization() &&
99  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createProbeDCEPass());
100 
101  if (opt.shouldDedup())
102  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDedupPass());
103 
104  if (opt.shouldRunWireDFT())
105  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createWireDFTPass());
106 
107  if (opt.shouldConvertVecOfBundle()) {
108  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypesPass(
110  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createVBToBVPass());
111  }
112 
113  if (!opt.shouldLowerMemories())
114  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
116 
117  // The input mlir file could be firrtl dialect so we might need to clean
118  // things up.
119  // pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerSignaturesPass());
120  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypesPass(
121  opt.getPreserveAggregate(), firrtl::PreserveAggregate::None));
122 
123  pm.nest<firrtl::CircuitOp>().nestAny().addPass(
125 
126  auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
127  modulePM.addPass(firrtl::createSFCCompatPass());
128  modulePM.addPass(firrtl::createLayerMergePass());
129  modulePM.addPass(firrtl::createLayerSinkPass());
130 
131  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerLayersPass());
132 
133  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInlinerPass());
134 
135  // Preset the random initialization parameters for each module. The current
136  // implementation assumes it can run at a time where every register is
137  // currently in the final module it will be emitted in, all registers have
138  // been created, and no registers have yet been removed.
139  if (opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg))
140  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
142 
143  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createCheckCombLoopsPass());
144 
145  // If we parsed a FIRRTL file and have optimizations enabled, clean it up.
146  if (!opt.shouldDisableOptimization())
147  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
149 
150  // Run the infer-rw pass, which merges read and write ports of a memory with
151  // mutually exclusive enables.
152  if (!opt.shouldDisableOptimization())
153  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
155 
157  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerMemoryPass());
158 
159  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createPrefixModulesPass());
160 
161  if (!opt.shouldDisableOptimization()) {
162  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstPropPass());
163 
164  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createHoistPassthroughPass(
165  /*hoistHWDrivers=*/!opt.shouldDisableOptimization() &&
167  // Cleanup after hoisting passthroughs, for separation-of-concerns.
168  pm.addPass(firrtl::createIMDeadCodeElimPass());
169  }
170 
171  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createAddSeqMemPortsPass());
172 
176 
177  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createExtractInstancesPass());
178 
179  // Run passes to resolve Grand Central features. This should run before
180  // BlackBoxReader because Grand Central needs to inform BlackBoxReader where
181  // certain black boxes should be placed. Note: all Grand Central Taps related
182  // collateral is resolved entirely by LowerAnnotations.
183  pm.addNestedPass<firrtl::CircuitOp>(
185 
186  // Read black box source files into the IR.
187  StringRef blackBoxRoot = opt.getBlackBoxRootPath().empty()
188  ? llvm::sys::path::parent_path(inputFilename)
189  : opt.getBlackBoxRootPath();
190  pm.nest<firrtl::CircuitOp>().addPass(
191  firrtl::createBlackBoxReaderPass(blackBoxRoot));
192 
193  // Run SymbolDCE as late as possible, but before InnerSymbolDCE. This is for
194  // hierpathop's and just for general cleanup.
195  pm.addNestedPass<firrtl::CircuitOp>(mlir::createSymbolDCEPass());
196 
197  // Run InnerSymbolDCE as late as possible, but before IMDCE.
198  pm.addPass(firrtl::createInnerSymbolDCEPass());
199 
200  // The above passes, IMConstProp in particular, introduce additional
201  // canonicalization opportunities that we should pick up here before we
202  // proceed to output-specific pipelines.
203  if (!opt.shouldDisableOptimization()) {
204  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
206  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
208  // Re-run IMConstProp to propagate constants produced by register
209  // optimizations.
210  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstPropPass());
211  pm.addPass(firrtl::createIMDeadCodeElimPass());
212  }
213 
214  if (opt.shouldEmitOMIR())
215  pm.nest<firrtl::CircuitOp>().addPass(
217 
218  // Always run this, required for legalization.
219  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
222 
223  if (!opt.shouldDisableOptimization())
224  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
226 
227  return success();
228 }
229 
230 LogicalResult firtool::populateLowFIRRTLToHW(mlir::PassManager &pm,
231  const FirtoolOptions &opt) {
232  // Remove TraceAnnotations and write their updated paths to an output
233  // annotation file.
234  pm.nest<firrtl::CircuitOp>().addPass(
236 
237  // Lower the ref.resolve and ref.send ops and remove the RefType ports.
238  // LowerToHW cannot handle RefType so, this pass must be run to remove all
239  // RefType ports and ops.
240  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerXMRPass());
241 
242  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerClassesPass());
243 
244  // Check for static asserts.
245  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
247 
250 
251  if (!opt.shouldDisableOptimization()) {
252  auto &modulePM = pm.nest<hw::HWModuleOp>();
253  modulePM.addPass(mlir::createCSEPass());
254  modulePM.addPass(createSimpleCanonicalizerPass());
255  }
256 
257  // Check inner symbols and inner refs.
259 
260  return success();
261 }
262 
263 LogicalResult firtool::populateHWToSV(mlir::PassManager &pm,
264  const FirtoolOptions &opt) {
265  if (opt.shouldExtractTestCode())
270 
273  {/*disableRegRandomization=*/!opt.isRandomEnabled(
274  FirtoolOptions::RandomKind::Reg),
275  /*disableMemRandomization=*/
276  !opt.isRandomEnabled(FirtoolOptions::RandomKind::Mem),
277  /*emitSeparateAlwaysBlocks=*/
279  pm.addNestedPass<hw::HWModuleOp>(circt::createLowerSimToSVPass());
280  pm.addNestedPass<hw::HWModuleOp>(createLowerVerifToSVPass());
281  pm.addPass(seq::createHWMemSimImplPass(
282  {/*disableMemRandomization=*/!opt.isRandomEnabled(
283  FirtoolOptions::RandomKind::Mem),
284  /*disableRegRandomization=*/
285  !opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg),
286  /*replSeqMem=*/opt.shouldReplicateSequentialMemories(),
287  /*readEnableMode=*/opt.shouldIgnoreReadEnableMemories()
288  ? seq::ReadEnableMode::Ignore
289  : seq::ReadEnableMode::Undefined,
290  /*addMuxPragmas=*/opt.shouldAddMuxPragmas(),
291  /*addVivadoRAMAddressConflictSynthesisBugWorkaround=*/
293 
294  // If enabled, run the optimizer.
295  if (!opt.shouldDisableOptimization()) {
296  auto &modulePM = pm.nest<hw::HWModuleOp>();
297  modulePM.addPass(mlir::createCSEPass());
298  modulePM.addPass(createSimpleCanonicalizerPass());
299  modulePM.addPass(mlir::createCSEPass());
300  modulePM.addPass(sv::createHWCleanupPass(
301  /*mergeAlwaysBlocks=*/!opt.shouldEmitSeparateAlwaysBlocks()));
302  }
303 
304  // Check inner symbols and inner refs.
306 
307  return success();
308 }
309 
310 namespace detail {
311 LogicalResult
312 populatePrepareForExportVerilog(mlir::PassManager &pm,
313  const firtool::FirtoolOptions &opt) {
314 
315  // Legalize unsupported operations within the modules.
316  pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModulesPass());
317 
318  // Tidy up the IR to improve verilog emission quality.
319  if (!opt.shouldDisableOptimization())
320  pm.nest<hw::HWModuleOp>().addPass(sv::createPrettifyVerilogPass());
321 
322  if (opt.shouldStripFirDebugInfo())
323  pm.addPass(circt::createStripDebugInfoWithPredPass([](mlir::Location loc) {
324  if (auto fileLoc = loc.dyn_cast<FileLineColLoc>())
325  return fileLoc.getFilename().getValue().ends_with(".fir");
326  return false;
327  }));
328 
329  if (opt.shouldStripDebugInfo())
331  [](mlir::Location loc) { return true; }));
332 
333  // Emit module and testbench hierarchy JSON files.
334  if (opt.shouldExportModuleHierarchy())
336 
337  // Check inner symbols and inner refs.
339 
340  return success();
341 }
342 } // namespace detail
343 
344 LogicalResult
345 firtool::populateExportVerilog(mlir::PassManager &pm, const FirtoolOptions &opt,
346  std::unique_ptr<llvm::raw_ostream> os) {
347  if (failed(::detail::populatePrepareForExportVerilog(pm, opt)))
348  return failure();
349 
350  pm.addPass(createExportVerilogPass(std::move(os)));
351  return success();
352 }
353 
354 LogicalResult firtool::populateExportVerilog(mlir::PassManager &pm,
355  const FirtoolOptions &opt,
356  llvm::raw_ostream &os) {
357  if (failed(::detail::populatePrepareForExportVerilog(pm, opt)))
358  return failure();
359 
360  pm.addPass(createExportVerilogPass(os));
361  return success();
362 }
363 
364 LogicalResult firtool::populateExportSplitVerilog(mlir::PassManager &pm,
365  const FirtoolOptions &opt,
366  llvm::StringRef directory) {
367  if (failed(::detail::populatePrepareForExportVerilog(pm, opt)))
368  return failure();
369 
370  pm.addPass(createExportSplitVerilogPass(directory));
371  return success();
372 }
373 
374 LogicalResult firtool::populateFinalizeIR(mlir::PassManager &pm,
375  const FirtoolOptions &opt) {
376  pm.addPass(firrtl::createFinalizeIRPass());
377  pm.addPass(om::createFreezePathsPass());
378 
379  return success();
380 }
381 
382 //===----------------------------------------------------------------------===//
383 // FIRTOOL CommandLine Options
384 //===----------------------------------------------------------------------===//
385 
386 namespace {
387 /// This struct contains command line options that can be used to initialize
388 /// various bits of a Firtool pipeline. This uses a struct wrapper to avoid the
389 /// need for global command line options.
390 struct FirtoolCmdOptions {
391  llvm::cl::opt<std::string> outputFilename{
392  "o",
393  llvm::cl::desc("Output filename, or directory for split output"),
394  llvm::cl::value_desc("filename"),
395  llvm::cl::init("-"),
396  };
397 
398  llvm::cl::opt<bool> disableAnnotationsUnknown{
399  "disable-annotation-unknown",
400  llvm::cl::desc("Ignore unknown annotations when parsing"),
401  llvm::cl::init(false)};
402 
403  llvm::cl::opt<bool> disableAnnotationsClassless{
404  "disable-annotation-classless",
405  llvm::cl::desc("Ignore annotations without a class when parsing"),
406  llvm::cl::init(false)};
407 
408  llvm::cl::opt<bool> lowerAnnotationsNoRefTypePorts{
409  "lower-annotations-no-ref-type-ports",
410  llvm::cl::desc(
411  "Create real ports instead of ref type ports when resolving "
412  "wiring problems inside the LowerAnnotations pass"),
413  llvm::cl::init(false), llvm::cl::Hidden};
414 
416  preserveAggregate{
417  "preserve-aggregate",
418  llvm::cl::desc("Specify input file format:"),
419  llvm::cl::values(
420  clEnumValN(circt::firrtl::PreserveAggregate::None, "none",
421  "Preserve no aggregate"),
422  clEnumValN(circt::firrtl::PreserveAggregate::OneDimVec, "1d-vec",
423  "Preserve only 1d vectors of ground type"),
424  clEnumValN(circt::firrtl::PreserveAggregate::Vec, "vec",
425  "Preserve only vectors"),
426  clEnumValN(circt::firrtl::PreserveAggregate::All, "all",
427  "Preserve vectors and bundles")),
429  };
430 
432  "preserve-values",
433  llvm::cl::desc("Specify the values which can be optimized away"),
434  llvm::cl::values(
435  clEnumValN(firrtl::PreserveValues::Strip, "strip",
436  "Strip all names. No name is preserved"),
437  clEnumValN(firrtl::PreserveValues::None, "none",
438  "Names could be preserved by best-effort unlike `strip`"),
439  clEnumValN(firrtl::PreserveValues::Named, "named",
440  "Preserve values with meaningful names"),
441  clEnumValN(firrtl::PreserveValues::All, "all",
442  "Preserve all values")),
443  llvm::cl::init(firrtl::PreserveValues::None)};
444 
445  llvm::cl::opt<bool> enableDebugInfo{
446  "g", llvm::cl::desc("Enable the generation of debug information"),
447  llvm::cl::init(false)};
448 
449  // Build mode options.
451  "O", llvm::cl::desc("Controls how much optimization should be performed"),
452  llvm::cl::values(clEnumValN(firtool::FirtoolOptions::BuildModeDebug,
453  "debug",
454  "Compile with only necessary optimizations"),
455  clEnumValN(firtool::FirtoolOptions::BuildModeRelease,
456  "release", "Compile with optimizations")),
457  llvm::cl::init(firtool::FirtoolOptions::BuildModeDefault)};
458 
459  llvm::cl::opt<bool> disableOptimization{
460  "disable-opt",
461  llvm::cl::desc("Disable optimizations"),
462  };
463 
465  "export-chisel-interface",
466  llvm::cl::desc("Generate a Scala Chisel interface to the top level "
467  "module of the firrtl circuit"),
468  llvm::cl::init(false)};
469 
470  llvm::cl::opt<std::string> chiselInterfaceOutDirectory{
471  "chisel-interface-out-dir",
472  llvm::cl::desc(
473  "The output directory for generated Chisel interface files"),
474  llvm::cl::init("")};
475 
476  llvm::cl::opt<bool> vbToBV{
477  "vb-to-bv",
478  llvm::cl::desc("Transform vectors of bundles to bundles of vectors"),
479  llvm::cl::init(false)};
480 
481  llvm::cl::opt<bool> noDedup{
482  "no-dedup",
483  llvm::cl::desc("Disable deduplication of structurally identical modules"),
484  llvm::cl::init(false)};
485 
486  llvm::cl::opt<bool> runWireDFT{
487  "run-wire-dft",
488  llvm::cl::desc("Run the now-deprecated WireDFT transform"),
489  llvm::cl::init(false),
490  llvm::cl::Hidden,
491  };
492 
494  "grand-central-companion-mode",
495  llvm::cl::desc("Specifies the handling of Grand Central companions"),
496  ::llvm::cl::values(
497  clEnumValN(firrtl::CompanionMode::Bind, "bind",
498  "Lower companion instances to SystemVerilog binds"),
499  clEnumValN(firrtl::CompanionMode::Instantiate, "instantiate",
500  "Instantiate companions in the design"),
501  clEnumValN(firrtl::CompanionMode::Drop, "drop",
502  "Remove companions from the design")),
503  llvm::cl::init(firrtl::CompanionMode::Bind),
504  llvm::cl::Hidden,
505  };
506 
507  llvm::cl::opt<bool> disableAggressiveMergeConnections{
508  "disable-aggressive-merge-connections",
509  llvm::cl::desc(
510  "Disable aggressive merge connections (i.e. merge all field-level "
511  "connections into bulk connections)"),
512  llvm::cl::init(false)};
513 
514  llvm::cl::opt<bool> disableHoistingHWPassthrough{
515  "disable-hoisting-hw-passthrough",
516  llvm::cl::desc("Disable hoisting HW passthrough signals"),
517  llvm::cl::init(true), llvm::cl::Hidden};
518 
519  llvm::cl::opt<bool> emitOMIR{
520  "emit-omir", llvm::cl::desc("Emit OMIR annotations to a JSON file"),
521  llvm::cl::init(true)};
522 
523  llvm::cl::opt<std::string> omirOutFile{
524  "output-omir", llvm::cl::desc("File name for the output omir"),
525  llvm::cl::init("")};
526 
527  llvm::cl::opt<bool> lowerMemories{
528  "lower-memories",
529  llvm::cl::desc("Lower memories to have memories with masks as an "
530  "array with one memory per ground type"),
531  llvm::cl::init(false)};
532 
533  llvm::cl::opt<std::string> blackBoxRootPath{
534  "blackbox-path",
535  llvm::cl::desc(
536  "Optional path to use as the root of black box annotations"),
537  llvm::cl::value_desc("path"),
538  llvm::cl::init(""),
539  };
540 
541  llvm::cl::opt<bool> replSeqMem{
542  "repl-seq-mem",
543  llvm::cl::desc("Replace the seq mem for macro replacement and emit "
544  "relevant metadata"),
545  llvm::cl::init(false)};
546 
547  llvm::cl::opt<std::string> replSeqMemFile{
548  "repl-seq-mem-file", llvm::cl::desc("File name for seq mem metadata"),
549  llvm::cl::init("")};
550 
551  llvm::cl::opt<bool> extractTestCode{
552  "extract-test-code", llvm::cl::desc("Run the extract test code pass"),
553  llvm::cl::init(false)};
554 
555  llvm::cl::opt<bool> ignoreReadEnableMem{
556  "ignore-read-enable-mem",
557  llvm::cl::desc("Ignore the read enable signal, instead of "
558  "assigning X on read disable"),
559  llvm::cl::init(false)};
560 
562  llvm::cl::desc(
563  "Disable random initialization code (may break semantics!)"),
564  llvm::cl::values(
565  clEnumValN(firtool::FirtoolOptions::RandomKind::Mem,
566  "disable-mem-randomization",
567  "Disable emission of memory randomization code"),
568  clEnumValN(firtool::FirtoolOptions::RandomKind::Reg,
569  "disable-reg-randomization",
570  "Disable emission of register randomization code"),
572  "disable-all-randomization",
573  "Disable emission of all randomization code")),
574  llvm::cl::init(firtool::FirtoolOptions::RandomKind::None)};
575 
576  llvm::cl::opt<std::string> outputAnnotationFilename{
577  "output-annotation-file",
578  llvm::cl::desc("Optional output annotation file"),
579  llvm::cl::CommaSeparated, llvm::cl::value_desc("filename")};
580 
581  llvm::cl::opt<bool> enableAnnotationWarning{
582  "warn-on-unprocessed-annotations",
583  llvm::cl::desc(
584  "Warn about annotations that were not removed by lower-to-hw"),
585  llvm::cl::init(false)};
586 
587  llvm::cl::opt<bool> addMuxPragmas{
588  "add-mux-pragmas",
589  llvm::cl::desc("Annotate mux pragmas for memory array access"),
590  llvm::cl::init(false)};
591 
592  llvm::cl::opt<bool> emitChiselAssertsAsSVA{
593  "emit-chisel-asserts-as-sva",
594  llvm::cl::desc("Convert all chisel asserts into SVA"),
595  llvm::cl::init(false)};
596 
597  llvm::cl::opt<bool> emitSeparateAlwaysBlocks{
598  "emit-separate-always-blocks",
599  llvm::cl::desc(
600  "Prevent always blocks from being merged and emit constructs into "
601  "separate always blocks whenever possible"),
602  llvm::cl::init(false)};
603 
604  llvm::cl::opt<bool> etcDisableInstanceExtraction{
605  "etc-disable-instance-extraction",
606  llvm::cl::desc("Disable extracting instances only that feed test code"),
607  llvm::cl::init(false)};
608 
609  llvm::cl::opt<bool> etcDisableRegisterExtraction{
610  "etc-disable-register-extraction",
611  llvm::cl::desc("Disable extracting registers that only feed test code"),
612  llvm::cl::init(false)};
613 
614  llvm::cl::opt<bool> etcDisableModuleInlining{
615  "etc-disable-module-inlining",
616  llvm::cl::desc("Disable inlining modules that only feed test code"),
617  llvm::cl::init(false)};
618 
619  llvm::cl::opt<bool> addVivadoRAMAddressConflictSynthesisBugWorkaround{
620  "add-vivado-ram-address-conflict-synthesis-bug-workaround",
621  llvm::cl::desc(
622  "Add a vivado specific SV attribute (* ram_style = "
623  "\"distributed\" *) to unpacked array registers as a workaronud "
624  "for a vivado synthesis bug that incorrectly modifies "
625  "address conflict behavivor of combinational memories"),
626  llvm::cl::init(false)};
627 
628  //===----------------------------------------------------------------------===
629  // External Clock Gate Options
630  //===----------------------------------------------------------------------===
631 
632  llvm::cl::opt<std::string> ckgModuleName{
633  "ckg-name", llvm::cl::desc("Clock gate module name"),
634  llvm::cl::init("EICG_wrapper")};
635 
636  llvm::cl::opt<std::string> ckgInputName{
637  "ckg-input", llvm::cl::desc("Clock gate input port name"),
638  llvm::cl::init("in")};
639 
640  llvm::cl::opt<std::string> ckgOutputName{
641  "ckg-output", llvm::cl::desc("Clock gate output port name"),
642  llvm::cl::init("out")};
643 
644  llvm::cl::opt<std::string> ckgEnableName{
645  "ckg-enable", llvm::cl::desc("Clock gate enable port name"),
646  llvm::cl::init("en")};
647 
648  llvm::cl::opt<std::string> ckgTestEnableName{
649  "ckg-test-enable",
650  llvm::cl::desc("Clock gate test enable port name (optional)"),
651  llvm::cl::init("test_en")};
652 
653  llvm::cl::opt<bool> exportModuleHierarchy{
654  "export-module-hierarchy",
655  llvm::cl::desc("Export module and instance hierarchy as JSON"),
656  llvm::cl::init(false)};
657 
658  llvm::cl::opt<bool> stripFirDebugInfo{
659  "strip-fir-debug-info",
660  llvm::cl::desc(
661  "Disable source fir locator information in output Verilog"),
662  llvm::cl::init(true)};
663 
664  llvm::cl::opt<bool> stripDebugInfo{
665  "strip-debug-info",
666  llvm::cl::desc("Disable source locator information in output Verilog"),
667  llvm::cl::init(false)};
668 
669  llvm::cl::opt<bool> fixupEICGWrapper{
670  "fixup-eicg-wrapper",
671  llvm::cl::desc("Lower `EICG_wrapper` modules into clock gate intrinsics"),
672  llvm::cl::init(false)};
673 };
674 } // namespace
675 
676 static llvm::ManagedStatic<FirtoolCmdOptions> clOptions;
677 
678 /// Register a set of useful command-line options that can be used to configure
679 /// various flags within the MLIRContext. These flags are used when constructing
680 /// an MLIR context for initialization.
682  // Make sure that the options struct has been initialized.
683  *clOptions;
684 }
685 
686 // Initialize the firtool options with defaults supplied by the cl::opts above.
688  : outputFilename("-"), disableAnnotationsUnknown(false),
689  disableAnnotationsClassless(false), lowerAnnotationsNoRefTypePorts(false),
690  preserveAggregate(firrtl::PreserveAggregate::None),
691  preserveMode(firrtl::PreserveValues::None), enableDebugInfo(false),
692  buildMode(BuildModeRelease), disableOptimization(false),
693  exportChiselInterface(false), chiselInterfaceOutDirectory(""),
694  vbToBV(false), noDedup(false), runWireDFT(false),
695  companionMode(firrtl::CompanionMode::Bind),
696  disableAggressiveMergeConnections(false),
697  disableHoistingHWPassthrough(true), emitOMIR(true), omirOutFile(""),
698  lowerMemories(false), blackBoxRootPath(""), replSeqMem(false),
699  replSeqMemFile(""), extractTestCode(false), ignoreReadEnableMem(false),
700  disableRandom(RandomKind::None), outputAnnotationFilename(""),
701  enableAnnotationWarning(false), addMuxPragmas(false),
702  emitChiselAssertsAsSVA(false), emitSeparateAlwaysBlocks(false),
703  etcDisableInstanceExtraction(false), etcDisableRegisterExtraction(false),
704  etcDisableModuleInlining(false),
705  addVivadoRAMAddressConflictSynthesisBugWorkaround(false),
706  ckgModuleName("EICG_wrapper"), ckgInputName("in"), ckgOutputName("out"),
707  ckgEnableName("en"), ckgTestEnableName("test_en"), ckgInstName("ckg"),
708  exportModuleHierarchy(false), stripFirDebugInfo(true),
709  stripDebugInfo(false), fixupEICGWrapper(false) {
710  if (!clOptions.isConstructed())
711  return;
712  outputFilename = clOptions->outputFilename;
713  disableAnnotationsUnknown = clOptions->disableAnnotationsUnknown;
714  disableAnnotationsClassless = clOptions->disableAnnotationsClassless;
715  lowerAnnotationsNoRefTypePorts = clOptions->lowerAnnotationsNoRefTypePorts;
716  preserveAggregate = clOptions->preserveAggregate;
717  preserveMode = clOptions->preserveMode;
718  enableDebugInfo = clOptions->enableDebugInfo;
719  buildMode = clOptions->buildMode;
720  disableOptimization = clOptions->disableOptimization;
721  exportChiselInterface = clOptions->exportChiselInterface;
722  chiselInterfaceOutDirectory = clOptions->chiselInterfaceOutDirectory;
723  vbToBV = clOptions->vbToBV;
724  noDedup = clOptions->noDedup;
725  runWireDFT = clOptions->runWireDFT;
726  companionMode = clOptions->companionMode;
728  clOptions->disableAggressiveMergeConnections;
729  disableHoistingHWPassthrough = clOptions->disableHoistingHWPassthrough;
730  emitOMIR = clOptions->emitOMIR;
731  omirOutFile = clOptions->omirOutFile;
732  lowerMemories = clOptions->lowerMemories;
733  blackBoxRootPath = clOptions->blackBoxRootPath;
734  replSeqMem = clOptions->replSeqMem;
735  replSeqMemFile = clOptions->replSeqMemFile;
736  extractTestCode = clOptions->extractTestCode;
737  ignoreReadEnableMem = clOptions->ignoreReadEnableMem;
738  disableRandom = clOptions->disableRandom;
739  outputAnnotationFilename = clOptions->outputAnnotationFilename;
740  enableAnnotationWarning = clOptions->enableAnnotationWarning;
741  addMuxPragmas = clOptions->addMuxPragmas;
742  emitChiselAssertsAsSVA = clOptions->emitChiselAssertsAsSVA;
743  emitSeparateAlwaysBlocks = clOptions->emitSeparateAlwaysBlocks;
744  etcDisableInstanceExtraction = clOptions->etcDisableInstanceExtraction;
745  etcDisableRegisterExtraction = clOptions->etcDisableRegisterExtraction;
746  etcDisableModuleInlining = clOptions->etcDisableModuleInlining;
748  clOptions->addVivadoRAMAddressConflictSynthesisBugWorkaround;
749  ckgModuleName = clOptions->ckgModuleName;
750  ckgInputName = clOptions->ckgInputName;
751  ckgOutputName = clOptions->ckgOutputName;
752  ckgEnableName = clOptions->ckgEnableName;
753  ckgTestEnableName = clOptions->ckgTestEnableName;
754  exportModuleHierarchy = clOptions->exportModuleHierarchy;
755  stripFirDebugInfo = clOptions->stripFirDebugInfo;
756  stripDebugInfo = clOptions->stripDebugInfo;
757  fixupEICGWrapper = clOptions->fixupEICGWrapper;
758 }
static LogicalResult exportChiselInterface(CircuitOp circuit, llvm::raw_ostream &os)
Exports a Chisel interface to the output stream.
static llvm::ManagedStatic< FirtoolCmdOptions > clOptions
Definition: Firtool.cpp:676
Set of options used to control the behavior of the firtool pipeline.
Definition: Firtool.h:29
bool shouldStripDebugInfo() const
Definition: Firtool.h:116
firrtl::PreserveAggregate::PreserveMode getPreserveAggregate() const
Definition: Firtool.h:64
bool shouldAddVivadoRAMAddressConflictSynthesisBugWorkaround() const
Definition: Firtool.h:128
firrtl::PreserveValues::PreserveMode preserveMode
Definition: Firtool.h:359
StringRef getOmirOutputFile() const
Definition: Firtool.h:54
bool isDefaultOutputFilename() const
Definition: Firtool.h:84
StringRef getOutputFilename() const
Definition: Firtool.h:53
bool shouldDisableAggressiveMergeConnections() const
Definition: Firtool.h:119
StringRef getReplaceSequentialMemoriesFile() const
Definition: Firtool.h:59
bool shouldDisableHoistingHWPassthrough() const
Definition: Firtool.h:103
bool addVivadoRAMAddressConflictSynthesisBugWorkaround
Definition: Firtool.h:388
bool shouldExportChiselInterface() const
Definition: Firtool.h:102
bool shouldExtractTestCode() const
Definition: Firtool.h:131
std::string chiselInterfaceOutDirectory
Definition: Firtool.h:364
bool shouldFixupEICGWrapper() const
Definition: Firtool.h:132
firrtl::PreserveValues::PreserveMode getPreserveMode() const
Definition: Firtool.h:41
StringRef getBlackBoxRootPath() const
Definition: Firtool.h:55
bool shouldDisableOptimization() const
Definition: Firtool.h:95
firrtl::CompanionMode getCompanionMode() const
Definition: Firtool.h:67
bool shouldDisableClasslessAnnotations() const
Definition: Firtool.h:88
bool shouldEmitChiselAssertsAsSVA() const
Definition: Firtool.h:123
bool shouldIgnoreReadEnableMemories() const
Definition: Firtool.h:100
bool isRandomEnabled(RandomKind kind) const
Definition: Firtool.h:37
bool shouldDisableUnknownAnnotations() const
Definition: Firtool.h:85
bool shouldAddMuxPragmas() const
Definition: Firtool.h:127
bool shouldEnableAnnotationWarning() const
Definition: Firtool.h:122
bool shouldReplicateSequentialMemories() const
Definition: Firtool.h:94
bool shouldEtcDisableInstanceExtraction() const
Definition: Firtool.h:107
bool shouldConvertVecOfBundle() const
Definition: Firtool.h:106
StringRef getOutputAnnotationFilename() const
Definition: Firtool.h:60
bool shouldStripFirDebugInfo() const
Definition: Firtool.h:117
bool shouldEtcDisableRegisterExtraction() const
Definition: Firtool.h:110
std::string outputAnnotationFilename
Definition: Firtool.h:380
firrtl::PreserveAggregate::PreserveMode preserveAggregate
Definition: Firtool.h:358
bool shouldLowerMemories() const
Definition: Firtool.h:96
bool shouldEtcDisableModuleInlining() const
Definition: Firtool.h:113
bool shouldLowerNoRefTypePortAnnotations() const
Definition: Firtool.h:91
bool shouldExportModuleHierarchy() const
Definition: Firtool.h:118
firrtl::CompanionMode companionMode
Definition: Firtool.h:368
bool shouldRunWireDFT() const
Definition: Firtool.h:98
seq::ExternalizeClockGateOptions getClockGateOptions() const
Definition: Firtool.h:69
bool shouldEnableDebugInfo() const
Definition: Firtool.h:99
bool shouldEmitSeparateAlwaysBlocks() const
Definition: Firtool.h:124
StringRef getChiselInterfaceOutputDirectory() const
Definition: Firtool.h:56
std::unique_ptr< mlir::Pass > createDedupPass()
Definition: Dedup.cpp:743
@ All
Preserve all aggregate values.
Definition: Passes.h:51
@ OneDimVec
Preserve only 1d vectors of ground type (e.g. UInt<2>[3]).
Definition: Passes.h:45
@ Vec
Preserve only vectors (e.g. UInt<2>[3][3]).
Definition: Passes.h:48
@ None
Don't preserve aggregate at all.
Definition: Passes.h:42
@ Strip
Strip all names. No name on declaration is preserved.
Definition: Passes.h:155
std::unique_ptr< mlir::Pass > createInferReadWritePass()
std::unique_ptr< mlir::Pass > createCheckCombLoopsPass()
std::unique_ptr< mlir::Pass > createFinalizeIRPass()
Definition: FinalizeIR.cpp:38
std::unique_ptr< mlir::Pass > createLowerFIRRTLTypesPass(PreserveAggregate::PreserveMode mode=PreserveAggregate::None, PreserveAggregate::PreserveMode memoryMode=PreserveAggregate::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createResolveTracesPass(mlir::StringRef outputAnnotationFilename="")
std::unique_ptr< mlir::Pass > createEmitOMIRPass(mlir::StringRef outputFilename="")
std::unique_ptr< mlir::Pass > createResolvePathsPass()
std::unique_ptr< mlir::Pass > createLowerSignaturesPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createVBToBVPass()
Definition: VBToBV.cpp:988
std::unique_ptr< mlir::Pass > createGrandCentralPass(CompanionMode companionMode=CompanionMode::Bind)
std::unique_ptr< mlir::Pass > createIMConstPropPass()
std::unique_ptr< mlir::Pass > createBlackBoxReaderPass(std::optional< mlir::StringRef > inputPrefix={})
std::unique_ptr< mlir::Pass > createCreateSiFiveMetadataPass(bool replSeqMem=false, mlir::StringRef replSeqMemFile="")
std::unique_ptr< mlir::Pass > createLayerMergePass()
Definition: LayerMerge.cpp:73
std::unique_ptr< mlir::Pass > createInlinerPass()
std::unique_ptr< mlir::Pass > createVectorizationPass()
std::unique_ptr< mlir::Pass > createLowerMemoryPass()
std::unique_ptr< mlir::Pass > createDropNamesPass(PreserveValues::PreserveMode mode=PreserveValues::None)
Definition: DropName.cpp:92
std::unique_ptr< mlir::Pass > createLowerLayersPass()
std::unique_ptr< mlir::Pass > createIMDeadCodeElimPass()
std::unique_ptr< mlir::Pass > createLowerIntrinsicsPass(bool fixupEICGWrapper=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLintingPass()
Definition: Lint.cpp:69
std::unique_ptr< mlir::Pass > createPassiveWiresPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createExtractInstancesPass()
std::unique_ptr< mlir::Pass > createLayerSinkPass()
Definition: LayerSink.cpp:52
std::unique_ptr< mlir::Pass > createHoistPassthroughPass(bool hoistHWDrivers=true)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createProbeDCEPass()
This is the pass constructor.
Definition: ProbeDCE.cpp:78
std::unique_ptr< mlir::Pass > createLowerCHIRRTLPass()
std::unique_ptr< mlir::Pass > createInnerSymbolDCEPass()
std::unique_ptr< mlir::Pass > createExpandWhensPass()
std::unique_ptr< mlir::Pass > createLowerXMRPass()
Definition: LowerXMR.cpp:843
std::unique_ptr< mlir::Pass > createInferWidthsPass()
std::unique_ptr< mlir::Pass > createMemToRegOfVecPass(bool replSeqMem=false, bool ignoreReadEnable=false)
std::unique_ptr< mlir::Pass > createLowerOpenAggsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createDropConstPass()
Definition: DropConst.cpp:96
std::unique_ptr< mlir::Pass > createSFCCompatPass()
Definition: SFCCompat.cpp:141
std::unique_ptr< mlir::Pass > createWireDFTPass()
Definition: WireDFT.cpp:547
std::unique_ptr< mlir::Pass > createPrefixModulesPass()
std::unique_ptr< mlir::Pass > createInjectDUTHierarchyPass()
std::unique_ptr< mlir::Pass > createRandomizeRegisterInitPass()
std::unique_ptr< mlir::Pass > createLowerClassesPass()
std::unique_ptr< mlir::Pass > createAddSeqMemPortsPass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLAnnotationsPass(bool ignoreUnhandledAnnotations=false, bool ignoreClasslessAnnotations=false, bool noRefTypePorts=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createRegisterOptimizerPass()
std::unique_ptr< mlir::Pass > createLowerMatchesPass()
std::unique_ptr< mlir::Pass > createMergeConnectionsPass(bool enableAggressiveMerging=false)
std::unique_ptr< mlir::Pass > createInferResetsPass()
std::unique_ptr< mlir::Pass > createFlattenMemoryPass()
std::unique_ptr< mlir::Pass > createMaterializeDebugInfoPass()
LogicalResult populateExportSplitVerilog(mlir::PassManager &pm, const FirtoolOptions &opt, llvm::StringRef directory)
Definition: Firtool.cpp:364
LogicalResult populateHWToSV(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:263
LogicalResult populateLowFIRRTLToHW(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:230
LogicalResult populateExportVerilog(mlir::PassManager &pm, const FirtoolOptions &opt, std::unique_ptr< llvm::raw_ostream > os)
Definition: Firtool.cpp:345
LogicalResult populatePreprocessTransforms(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:26
void registerFirtoolCLOptions()
Register a set of useful command-line options that can be used to configure various flags within the ...
Definition: Firtool.cpp:681
LogicalResult populateFinalizeIR(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:374
LogicalResult populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm, const FirtoolOptions &opt, StringRef inputFilename)
Definition: Firtool.cpp:45
std::unique_ptr< mlir::Pass > createVerifyInnerRefNamespacePass()
std::unique_ptr< mlir::Pass > createFreezePathsPass()
std::unique_ptr< mlir::Pass > createHWMemSimImplPass(const HWMemSimImplOptions &options={})
std::unique_ptr< mlir::Pass > createExternalizeClockGatePass(const ExternalizeClockGateOptions &options={})
std::unique_ptr< mlir::Pass > createHWExportModuleHierarchyPass()
std::unique_ptr< mlir::Pass > createSVExtractTestCodePass(bool disableInstanceExtraction=false, bool disableRegisterExtraction=false, bool disableModuleInlining=false)
std::unique_ptr< mlir::Pass > createHWLegalizeModulesPass()
std::unique_ptr< mlir::Pass > createPrettifyVerilogPass()
std::unique_ptr< mlir::Pass > createHWCleanupPass(bool mergeAlwaysBlocks=true)
Definition: HWCleanup.cpp:245
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
Definition: DebugAnalysis.h:21
std::unique_ptr< mlir::Pass > createExportSplitChiselInterfacePass(mlir::StringRef outputDirectory="./")
std::unique_ptr< mlir::Pass > createLowerFIRRTLToHWPass(bool enableAnnotationWarning=false, bool emitChiselAssertsAsSVA=false)
This is the pass constructor.
Definition: LowerToHW.cpp:518
std::unique_ptr< mlir::Pass > createExportVerilogPass(std::unique_ptr< llvm::raw_ostream > os)
std::unique_ptr< mlir::Pass > createExportChiselInterfacePass(llvm::raw_ostream &os)
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< OperationPass< hw::HWModuleOp > > createLowerVerifToSVPass()
Create the Verif to SV conversion pass.
Definition: VerifToSV.cpp:153
std::unique_ptr< mlir::Pass > createLowerSeqToSVPass(const LowerSeqToSVOptions &options={})
Definition: SeqToSV.cpp:576
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
Definition: SimToSV.cpp:133
std::unique_ptr< Pass > createSimpleCanonicalizerPass()
Create a simple canonicalizer pass.
Definition: Passes.cpp:15
std::unique_ptr< mlir::Pass > createStripDebugInfoWithPredPass(const std::function< bool(mlir::Location)> &pred)
Creates a pass to strip debug information from a function.
LogicalResult populatePrepareForExportVerilog(mlir::PassManager &pm, const firtool::FirtoolOptions &opt)
Definition: Firtool.cpp:312