19 #include "mlir/Transforms/Passes.h"
20 #include "llvm/Support/FileSystem.h"
21 #include "llvm/Support/Path.h"
24 using namespace circt;
39 pm.nest<firrtl::CircuitOp>().addNestedPass<firrtl::FModuleOp>(
42 pm.nest<firrtl::CircuitOp>().addPass(
44 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
52 StringRef inputFilename) {
57 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
60 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
64 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
65 mlir::createCSEPass());
67 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
72 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
78 pm.nest<firrtl::CircuitOp>().addPass(
91 pm.nest<firrtl::CircuitOp>().addPass(
113 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
122 pm.nest<firrtl::CircuitOp>().nestAny().addPass(
125 auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
139 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
146 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
152 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
161 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
186 pm.addNestedPass<firrtl::CircuitOp>(
191 ? llvm::sys::path::parent_path(inputFilename)
193 pm.nest<firrtl::CircuitOp>().addPass(
198 pm.addNestedPass<firrtl::CircuitOp>(mlir::createSymbolDCEPass());
207 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
209 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
218 pm.nest<firrtl::CircuitOp>().addPass(
222 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
227 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
237 pm.nest<firrtl::CircuitOp>().addPass(
248 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
256 modulePM.addPass(mlir::createCSEPass());
278 FirtoolOptions::RandomKind::Reg),
286 FirtoolOptions::RandomKind::Mem),
291 ? seq::ReadEnableMode::Ignore
292 : seq::ReadEnableMode::Undefined,
300 modulePM.addPass(mlir::createCSEPass());
302 modulePM.addPass(mlir::createCSEPass());
327 if (auto fileLoc = loc.dyn_cast<FileLineColLoc>())
328 return fileLoc.getFilename().getValue().ends_with(
".fir");
334 [](mlir::Location loc) { return true; }));
349 std::unique_ptr<llvm::raw_ostream> os) {
359 llvm::raw_ostream &os) {
369 llvm::StringRef directory) {
393 struct FirtoolCmdOptions {
396 llvm::cl::desc(
"Output filename, or directory for split output"),
397 llvm::cl::value_desc(
"filename"),
402 "disable-annotation-unknown",
403 llvm::cl::desc(
"Ignore unknown annotations when parsing"),
404 llvm::cl::init(
false)};
407 "disable-annotation-classless",
408 llvm::cl::desc(
"Ignore annotations without a class when parsing"),
409 llvm::cl::init(
false)};
412 "lower-annotations-no-ref-type-ports",
414 "Create real ports instead of ref type ports when resolving "
415 "wiring problems inside the LowerAnnotations pass"),
416 llvm::cl::init(
false), llvm::cl::Hidden};
420 "preserve-aggregate",
421 llvm::cl::desc(
"Specify input file format:"),
424 "Preserve no aggregate"),
426 "Preserve only 1d vectors of ground type"),
428 "Preserve only vectors"),
430 "Preserve vectors and bundles")),
436 llvm::cl::desc(
"Specify the values which can be optimized away"),
439 "Strip all names. No name is preserved"),
440 clEnumValN(firrtl::PreserveValues::None,
"none",
441 "Names could be preserved by best-effort unlike `strip`"),
443 "Preserve values with meaningful names"),
445 "Preserve all values")),
446 llvm::cl::init(firrtl::PreserveValues::None)};
449 "g", llvm::cl::desc(
"Enable the generation of debug information"),
450 llvm::cl::init(
false)};
454 "O", llvm::cl::desc(
"Controls how much optimization should be performed"),
455 llvm::cl::values(clEnumValN(firtool::FirtoolOptions::BuildModeDebug,
457 "Compile with only necessary optimizations"),
458 clEnumValN(firtool::FirtoolOptions::BuildModeRelease,
459 "release",
"Compile with optimizations")),
460 llvm::cl::init(firtool::FirtoolOptions::BuildModeDefault)};
464 llvm::cl::desc(
"Disable optimizations"),
468 "export-chisel-interface",
469 llvm::cl::desc(
"Generate a Scala Chisel interface to the top level "
470 "module of the firrtl circuit"),
471 llvm::cl::init(
false)};
474 "chisel-interface-out-dir",
476 "The output directory for generated Chisel interface files"),
481 llvm::cl::desc(
"Transform vectors of bundles to bundles of vectors"),
482 llvm::cl::init(
false)};
486 llvm::cl::desc(
"Disable deduplication of structurally identical modules"),
487 llvm::cl::init(
false)};
490 "grand-central-companion-mode",
491 llvm::cl::desc(
"Specifies the handling of Grand Central companions"),
493 clEnumValN(firrtl::CompanionMode::Bind,
"bind",
494 "Lower companion instances to SystemVerilog binds"),
495 clEnumValN(firrtl::CompanionMode::Instantiate,
"instantiate",
496 "Instantiate companions in the design"),
497 clEnumValN(firrtl::CompanionMode::Drop,
"drop",
498 "Remove companions from the design")),
499 llvm::cl::init(firrtl::CompanionMode::Bind),
504 "disable-aggressive-merge-connections",
506 "Disable aggressive merge connections (i.e. merge all field-level "
507 "connections into bulk connections)"),
508 llvm::cl::init(
false)};
511 "disable-hoisting-hw-passthrough",
512 llvm::cl::desc(
"Disable hoisting HW passthrough signals"),
513 llvm::cl::init(
true), llvm::cl::Hidden};
516 "emit-omir", llvm::cl::desc(
"Emit OMIR annotations to a JSON file"),
517 llvm::cl::init(
true)};
520 "output-omir", llvm::cl::desc(
"File name for the output omir"),
525 llvm::cl::desc(
"Lower memories to have memories with masks as an "
526 "array with one memory per ground type"),
527 llvm::cl::init(
false)};
532 "Optional path to use as the root of black box annotations"),
533 llvm::cl::value_desc(
"path"),
539 llvm::cl::desc(
"Replace the seq mem for macro replacement and emit "
540 "relevant metadata"),
541 llvm::cl::init(
false)};
544 "repl-seq-mem-file", llvm::cl::desc(
"File name for seq mem metadata"),
548 "extract-test-code", llvm::cl::desc(
"Run the extract test code pass"),
549 llvm::cl::init(
false)};
552 "ignore-read-enable-mem",
553 llvm::cl::desc(
"Ignore the read enable signal, instead of "
554 "assigning X on read disable"),
555 llvm::cl::init(
false)};
559 "Disable random initialization code (may break semantics!)"),
561 clEnumValN(firtool::FirtoolOptions::RandomKind::Mem,
562 "disable-mem-randomization",
563 "Disable emission of memory randomization code"),
564 clEnumValN(firtool::FirtoolOptions::RandomKind::Reg,
565 "disable-reg-randomization",
566 "Disable emission of register randomization code"),
568 "disable-all-randomization",
569 "Disable emission of all randomization code")),
570 llvm::cl::init(firtool::FirtoolOptions::RandomKind::None)};
573 "output-annotation-file",
574 llvm::cl::desc(
"Optional output annotation file"),
575 llvm::cl::CommaSeparated, llvm::cl::value_desc(
"filename")};
578 "warn-on-unprocessed-annotations",
580 "Warn about annotations that were not removed by lower-to-hw"),
581 llvm::cl::init(
false)};
585 llvm::cl::desc(
"Annotate mux pragmas for memory array access"),
586 llvm::cl::init(
false)};
589 "verification-flavor",
590 llvm::cl::desc(
"Specify a verification flavor used in LowerFIRRTLToHW"),
592 clEnumValN(firrtl::VerificationFlavor::None,
"none",
593 "Use the flavor specified by the op"),
594 clEnumValN(firrtl::VerificationFlavor::IfElseFatal,
"if-else-fatal",
595 "Use Use `if(cond) else $fatal(..)` format"),
596 clEnumValN(firrtl::VerificationFlavor::Immediate,
"immediate",
597 "Use immediate verif statements"),
598 clEnumValN(firrtl::VerificationFlavor::SVA,
"sva",
"Use SVA")),
599 llvm::cl::init(firrtl::VerificationFlavor::None)};
602 "emit-separate-always-blocks",
604 "Prevent always blocks from being merged and emit constructs into "
605 "separate always blocks whenever possible"),
606 llvm::cl::init(
false)};
609 "etc-disable-instance-extraction",
610 llvm::cl::desc(
"Disable extracting instances only that feed test code"),
611 llvm::cl::init(
false)};
614 "etc-disable-register-extraction",
615 llvm::cl::desc(
"Disable extracting registers that only feed test code"),
616 llvm::cl::init(
false)};
619 "etc-disable-module-inlining",
620 llvm::cl::desc(
"Disable inlining modules that only feed test code"),
621 llvm::cl::init(
false)};
624 "add-vivado-ram-address-conflict-synthesis-bug-workaround",
626 "Add a vivado specific SV attribute (* ram_style = "
627 "\"distributed\" *) to unpacked array registers as a workaronud "
628 "for a vivado synthesis bug that incorrectly modifies "
629 "address conflict behavivor of combinational memories"),
630 llvm::cl::init(
false)};
637 "ckg-name", llvm::cl::desc(
"Clock gate module name"),
638 llvm::cl::init(
"EICG_wrapper")};
641 "ckg-input", llvm::cl::desc(
"Clock gate input port name"),
642 llvm::cl::init(
"in")};
645 "ckg-output", llvm::cl::desc(
"Clock gate output port name"),
646 llvm::cl::init(
"out")};
649 "ckg-enable", llvm::cl::desc(
"Clock gate enable port name"),
650 llvm::cl::init(
"en")};
654 llvm::cl::desc(
"Clock gate test enable port name (optional)"),
655 llvm::cl::init(
"test_en")};
658 "export-module-hierarchy",
659 llvm::cl::desc(
"Export module and instance hierarchy as JSON"),
660 llvm::cl::init(
false)};
663 "strip-fir-debug-info",
665 "Disable source fir locator information in output Verilog"),
666 llvm::cl::init(
true)};
670 llvm::cl::desc(
"Disable source locator information in output Verilog"),
671 llvm::cl::init(
false)};
674 "fixup-eicg-wrapper",
675 llvm::cl::desc(
"Lower `EICG_wrapper` modules into clock gate intrinsics"),
676 llvm::cl::init(
false)};
679 "add-companion-assume",
680 llvm::cl::desc(
"Add companion assumes to assertions"),
681 llvm::cl::init(
false)};
685 static llvm::ManagedStatic<FirtoolCmdOptions>
clOptions;
697 : outputFilename(
"-"), disableAnnotationsUnknown(false),
698 disableAnnotationsClassless(false), lowerAnnotationsNoRefTypePorts(false),
699 preserveAggregate(firrtl::PreserveAggregate::None),
700 preserveMode(firrtl::PreserveValues::None), enableDebugInfo(false),
701 buildMode(BuildModeRelease), disableOptimization(false),
703 vbToBV(false), noDedup(false), companionMode(firrtl::
CompanionMode::Bind),
704 disableAggressiveMergeConnections(false),
705 disableHoistingHWPassthrough(true), emitOMIR(true), omirOutFile(
""),
706 lowerMemories(false), blackBoxRootPath(
""), replSeqMem(false),
707 replSeqMemFile(
""), extractTestCode(false), ignoreReadEnableMem(false),
708 disableRandom(
RandomKind::None), outputAnnotationFilename(
""),
709 enableAnnotationWarning(false), addMuxPragmas(false),
711 emitSeparateAlwaysBlocks(false), etcDisableInstanceExtraction(false),
712 etcDisableRegisterExtraction(false), etcDisableModuleInlining(false),
713 addVivadoRAMAddressConflictSynthesisBugWorkaround(false),
714 ckgModuleName(
"EICG_wrapper"), ckgInputName(
"in"), ckgOutputName(
"out"),
715 ckgEnableName(
"en"), ckgTestEnableName(
"test_en"), ckgInstName(
"ckg"),
716 exportModuleHierarchy(false), stripFirDebugInfo(true),
717 stripDebugInfo(false), fixupEICGWrapper(false),
718 addCompanionAssume(false) {
736 clOptions->disableAggressiveMergeConnections;
756 clOptions->addVivadoRAMAddressConflictSynthesisBugWorkaround;
static LogicalResult exportChiselInterface(CircuitOp circuit, llvm::raw_ostream &os)
Exports a Chisel interface to the output stream.
std::unique_ptr< mlir::Pass > createDedupPass()
@ All
Preserve all aggregate values.
@ OneDimVec
Preserve only 1d vectors of ground type (e.g. UInt<2>[3]).
@ Vec
Preserve only vectors (e.g. UInt<2>[3][3]).
@ None
Don't preserve aggregate at all.
@ Strip
Strip all names. No name on declaration is preserved.
std::unique_ptr< mlir::Pass > createInferReadWritePass()
std::unique_ptr< mlir::Pass > createCheckCombLoopsPass()
std::unique_ptr< mlir::Pass > createFinalizeIRPass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLTypesPass(PreserveAggregate::PreserveMode mode=PreserveAggregate::None, PreserveAggregate::PreserveMode memoryMode=PreserveAggregate::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createResolveTracesPass(mlir::StringRef outputAnnotationFilename="")
std::unique_ptr< mlir::Pass > createEmitOMIRPass(mlir::StringRef outputFilename="")
std::unique_ptr< mlir::Pass > createResolvePathsPass()
std::unique_ptr< mlir::Pass > createLowerSignaturesPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createVBToBVPass()
std::unique_ptr< mlir::Pass > createGrandCentralPass(CompanionMode companionMode=CompanionMode::Bind)
std::unique_ptr< mlir::Pass > createLowerIntmodulesPass(bool fixupEICGWrapper=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createIMConstPropPass()
std::unique_ptr< mlir::Pass > createBlackBoxReaderPass(std::optional< mlir::StringRef > inputPrefix={})
std::unique_ptr< mlir::Pass > createCreateCompanionAssume()
std::unique_ptr< mlir::Pass > createCreateSiFiveMetadataPass(bool replSeqMem=false, mlir::StringRef replSeqMemFile="")
std::unique_ptr< mlir::Pass > createLayerMergePass()
std::unique_ptr< mlir::Pass > createInlinerPass()
std::unique_ptr< mlir::Pass > createVectorizationPass()
std::unique_ptr< mlir::Pass > createLowerMemoryPass()
std::unique_ptr< mlir::Pass > createDropNamesPass(PreserveValues::PreserveMode mode=PreserveValues::None)
std::unique_ptr< mlir::Pass > createLowerLayersPass()
std::unique_ptr< mlir::Pass > createIMDeadCodeElimPass()
std::unique_ptr< mlir::Pass > createLintingPass()
std::unique_ptr< mlir::Pass > createPassiveWiresPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createExtractInstancesPass()
std::unique_ptr< mlir::Pass > createLayerSinkPass()
std::unique_ptr< mlir::Pass > createHoistPassthroughPass(bool hoistHWDrivers=true)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createProbeDCEPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLowerCHIRRTLPass()
std::unique_ptr< mlir::Pass > createInnerSymbolDCEPass()
std::unique_ptr< mlir::Pass > createExpandWhensPass()
std::unique_ptr< mlir::Pass > createLowerXMRPass()
std::unique_ptr< mlir::Pass > createLowerIntrinsicsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createInferWidthsPass()
std::unique_ptr< mlir::Pass > createMemToRegOfVecPass(bool replSeqMem=false, bool ignoreReadEnable=false)
std::unique_ptr< mlir::Pass > createLowerOpenAggsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createDropConstPass()
std::unique_ptr< mlir::Pass > createSFCCompatPass()
std::unique_ptr< mlir::Pass > createPrefixModulesPass()
std::unique_ptr< mlir::Pass > createInjectDUTHierarchyPass()
std::unique_ptr< mlir::Pass > createRandomizeRegisterInitPass()
std::unique_ptr< mlir::Pass > createLowerClassesPass()
std::unique_ptr< mlir::Pass > createAddSeqMemPortsPass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLAnnotationsPass(bool ignoreUnhandledAnnotations=false, bool ignoreClasslessAnnotations=false, bool noRefTypePorts=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createRegisterOptimizerPass()
std::unique_ptr< mlir::Pass > createLowerMatchesPass()
std::unique_ptr< mlir::Pass > createMergeConnectionsPass(bool enableAggressiveMerging=false)
std::unique_ptr< mlir::Pass > createInferResetsPass()
std::unique_ptr< mlir::Pass > createFlattenMemoryPass()
std::unique_ptr< mlir::Pass > createMaterializeDebugInfoPass()
std::unique_ptr< mlir::Pass > createVerifyInnerRefNamespacePass()
std::unique_ptr< mlir::Pass > createFreezePathsPass()
std::unique_ptr< mlir::Pass > createHWMemSimImplPass(const HWMemSimImplOptions &options={})
std::unique_ptr< mlir::Pass > createExternalizeClockGatePass(const ExternalizeClockGateOptions &options={})
std::unique_ptr< mlir::Pass > createHWExportModuleHierarchyPass()
std::unique_ptr< mlir::Pass > createSVExtractTestCodePass(bool disableInstanceExtraction=false, bool disableRegisterExtraction=false, bool disableModuleInlining=false)
std::unique_ptr< mlir::Pass > createHWLegalizeModulesPass()
std::unique_ptr< mlir::Pass > createPrettifyVerilogPass()
std::unique_ptr< mlir::Pass > createHWCleanupPass(bool mergeAlwaysBlocks=true)
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createExportSplitChiselInterfacePass(mlir::StringRef outputDirectory="./")
std::unique_ptr< mlir::Pass > createExportVerilogPass(std::unique_ptr< llvm::raw_ostream > os)
std::unique_ptr< mlir::Pass > createExportChiselInterfacePass(llvm::raw_ostream &os)
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< OperationPass< hw::HWModuleOp > > createLowerVerifToSVPass()
Create the Verif to SV conversion pass.
std::unique_ptr< mlir::Pass > createLowerSeqToSVPass(const LowerSeqToSVOptions &options={})
std::unique_ptr< mlir::Pass > createLowerFIRRTLToHWPass(bool enableAnnotationWarning=false, firrtl::VerificationFlavor assertionFlavor=firrtl::VerificationFlavor::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
std::unique_ptr< Pass > createSimpleCanonicalizerPass()
Create a simple canonicalizer pass.
std::unique_ptr< mlir::Pass > createStripDebugInfoWithPredPass(const std::function< bool(mlir::Location)> &pred)
Creates a pass to strip debug information from a function.
LogicalResult populatePrepareForExportVerilog(mlir::PassManager &pm, const firtool::FirtoolOptions &opt)