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Firtool.cpp
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1//===- Firtool.cpp - Definitions for the firtool pipeline setup -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
20#include "mlir/Transforms/Passes.h"
21#include "llvm/Support/FileSystem.h"
22#include "llvm/Support/Path.h"
23
24using namespace llvm;
25using namespace circt;
26
27LogicalResult firtool::populatePreprocessTransforms(mlir::PassManager &pm,
28 const FirtoolOptions &opt) {
29 pm.nest<firrtl::CircuitOp>().addPass(
30 firrtl::createCheckRecursiveInstantiation());
31 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createCheckLayers());
32 // Legalize away "open" aggregates to hw-only versions.
33 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerOpenAggs());
34
35 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createResolvePaths());
36
37 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerFIRRTLAnnotations(
38 {/*ignoreAnnotationClassless=*/opt.shouldDisableClasslessAnnotations(),
39 /*ignoreAnnotationUnknown=*/opt.shouldDisableUnknownAnnotations(),
40 /*noRefTypePorts=*/opt.shouldLowerNoRefTypePortAnnotations(),
41 /*allowAddingPortsOnPublic=*/opt.shouldAllowAddingPortsOnPublic()}));
42
43 if (opt.shouldEnableDebugInfo())
44 pm.nest<firrtl::CircuitOp>().addNestedPass<firrtl::FModuleOp>(
45 firrtl::createMaterializeDebugInfo());
46
47 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerIntmodules(
48 {/*fixupEICGWrapper=*/opt.shouldFixupEICGWrapper()}));
49 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
50 firrtl::createLowerIntrinsics());
51
52 return success();
53}
54
55LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
56 const FirtoolOptions &opt) {
57 // TODO: Ensure instance graph and other passes can handle instance choice
58 // then run this pass after all diagnostic passes have run.
59 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createSpecializeOption(
60 {/*selectDefaultInstanceChoice*/ opt
62 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerSignatures());
63
64 // This pass is _not_ idempotent. It preserves its controlling annotation for
65 // use by ExtractInstances. This pass should be run before ExtractInstances.
66 //
67 // TODO: This pass should be deleted.
68 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInjectDUTHierarchy());
69
70 if (!opt.shouldDisableOptimization()) {
72 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
73 mlir::createCSEPass());
74 else
75 pm.nest<firrtl::CircuitOp>().nestAny().addPass(mlir::createCSEPass());
76 }
77
78 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
79 firrtl::createPassiveWires());
80
81 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
82 firrtl::createDropName({/*preserveMode=*/opt.getPreserveMode()}));
83
84 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
85 firrtl::createLowerCHIRRTLPass());
86
87 // Run LowerMatches before InferWidths, as the latter does not support the
88 // match statement, but it does support what they lower to.
89 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
90 firrtl::createLowerMatches());
91
92 // Width inference creates canonicalization opportunities.
93 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferWidths());
94
95 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createMemToRegOfVec(
96 {/*replSeqMem=*/opt.shouldReplaceSequentialMemories(),
97 /*replSeqMemFile=*/opt.shouldIgnoreReadEnableMemories()}));
98
99 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferResets());
100
101 if (opt.shouldExportChiselInterface()) {
102 StringRef outdir = opt.getChiselInterfaceOutputDirectory();
103 if (opt.isDefaultOutputFilename() && outdir.empty()) {
104 pm.nest<firrtl::CircuitOp>().addPass(createExportChiselInterfacePass());
105 } else {
106 if (outdir.empty())
107 outdir = opt.getOutputFilename();
108 pm.nest<firrtl::CircuitOp>().addPass(
110 }
111 }
112
113 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDropConst());
114
115 if (opt.shouldDedup())
116 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDedup());
117
118 if (opt.shouldConvertVecOfBundle()) {
119 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypes(
120 {/*preserveAggregate=*/firrtl::PreserveAggregate::All,
121 /*preserveMemories*/ firrtl::PreserveAggregate::All}));
122 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createVBToBV());
123 }
124
125 if (!opt.shouldLowerMemories())
126 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
127 firrtl::createFlattenMemory());
128
129 // The input mlir file could be firrtl dialect so we might need to clean
130 // things up.
131 // pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerSignaturesPass());
132 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypes(
133 {/*preserveAggregate=*/opt.getPreserveAggregate(),
134 /*preserveMemory=*/firrtl::PreserveAggregate::None}));
135
136 {
137 auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
138 modulePM.addPass(firrtl::createExpandWhens());
139 modulePM.addPass(firrtl::createSFCCompat());
140 }
141
142 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createCheckCombLoops());
143
144 // Must run this pass after all diagnostic passes have run, otherwise it can
145 // hide errors.
146 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createSpecializeLayers());
147
148 // Run after inference, layer specialization.
150 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createProbesToSignals());
151
152 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInliner());
153
154 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
155 firrtl::createLayerMerge());
156
157 // Preset the random initialization parameters for each module. The current
158 // implementation assumes it can run at a time where every register is
159 // currently in the final module it will be emitted in, all registers have
160 // been created, and no registers have yet been removed.
161 if (opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg))
162 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
163 firrtl::createRandomizeRegisterInit());
164
165 // If we parsed a FIRRTL file and have optimizations enabled, clean it up.
166 if (!opt.shouldDisableOptimization())
167 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
169
170 // Run the infer-rw pass, which merges read and write ports of a memory with
171 // mutually exclusive enables.
172 if (!opt.shouldDisableOptimization())
173 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
174 firrtl::createInferReadWrite());
175
177 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerMemory());
178
179 if (opt.shouldAddCompanionAssume())
180 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
181 circt::firrtl::createCreateCompanionAssume());
182
183 if (!opt.shouldDisableOptimization())
184 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstProp());
185
186 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createAddSeqMemPorts());
187
188 pm.addPass(firrtl::createCreateSiFiveMetadata(
189 {/*replSeqMem=*/opt.shouldReplaceSequentialMemories(),
190 /*replSeqMemFile=*/opt.getReplaceSequentialMemoriesFile().str()}));
191
192 // This pass must be run after InjectDUTHierarchy.
193 //
194 // TODO: This pass should be deleted along with InjectDUTHierarchy.
195 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createExtractInstances());
196
197 // Run SymbolDCE as late as possible, but before InnerSymbolDCE. This is for
198 // hierpathop's and just for general cleanup.
199 pm.addNestedPass<firrtl::CircuitOp>(mlir::createSymbolDCEPass());
200
201 // Run InnerSymbolDCE as late as possible, but before IMDCE.
202 pm.addPass(firrtl::createInnerSymbolDCE());
203
204 // The above passes, IMConstProp in particular, introduce additional
205 // canonicalization opportunities that we should pick up here before we
206 // proceed to output-specific pipelines.
207 if (!opt.shouldDisableOptimization()) {
209 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
210 circt::firrtl::createEliminateWires());
211 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
213 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
214 circt::firrtl::createRegisterOptimizer());
215 // Re-run IMConstProp to propagate constants produced by register
216 // optimizations.
217 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstProp());
218 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
220 pm.addPass(firrtl::createIMDeadCodeElim());
221 }
222
223 // Always run this, required for legalization.
224 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
225 firrtl::createMergeConnections(
226 {/*enableAggressiveMergin=*/!opt
228
229 if (!opt.shouldDisableOptimization())
230 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
231 firrtl::createVectorization());
232
233 return success();
234}
235
236LogicalResult firtool::populateLowFIRRTLToHW(mlir::PassManager &pm,
237 const FirtoolOptions &opt,
238 StringRef inputFilename) {
239 // Run layersink immediately before LowerXMR. LowerXMR will "freeze" the
240 // location of probed objects by placing symbols on them. Run layersink first
241 // so that probed objects can be sunk if possible.
243 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLayerSink());
244
245 // Lower the ref.resolve and ref.send ops and remove the RefType ports.
246 // LowerToHW cannot handle RefType so, this pass must be run to remove all
247 // RefType ports and ops.
248 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerXMR());
249
250 // Layer lowering passes. Move operations into layers when possible and
251 // remove layers by converting them to other constructs. This lowering
252 // process can create a few optimization opportunities.
253 //
254 // TODO: Improve LowerLayers to avoid the need for canonicalization. See:
255 // https://github.com/llvm/circt/issues/7896
256
257 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerLayers());
258 if (!opt.shouldDisableOptimization())
259 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
261
262 auto outputFilename = opt.getOutputFilename();
263 if (outputFilename == "-")
264 outputFilename = "";
265
266 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createAssignOutputDirs(
267 {/*outputDirOption=*/outputFilename.str()}));
268
269 // Run passes to resolve Grand Central features. This should run before
270 // BlackBoxReader because Grand Central needs to inform BlackBoxReader where
271 // certain black boxes should be placed. Note: all Grand Central Taps related
272 // collateral is resolved entirely by LowerAnnotations.
273 // Run this after output directories are (otherwise) assigned,
274 // so generated interfaces can be appropriately marked.
275 pm.addNestedPass<firrtl::CircuitOp>(
276 firrtl::createGrandCentral({/*companionMode=*/opt.getCompanionMode()}));
277
278 // Read black box source files into the IR.
279 StringRef blackBoxRoot = opt.getBlackBoxRootPath().empty()
280 ? llvm::sys::path::parent_path(inputFilename)
281 : opt.getBlackBoxRootPath();
282 pm.nest<firrtl::CircuitOp>().addPass(
283 firrtl::createBlackBoxReader({/*inputPrefix=*/blackBoxRoot.str()}));
284
285 // Remove TraceAnnotations and write their updated paths to an output
286 // annotation file.
287 pm.nest<firrtl::CircuitOp>().addPass(
288 firrtl::createResolveTraces({opt.getOutputAnnotationFilename().str()}));
289
290 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerDPI());
291 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerClasses());
292 pm.nest<firrtl::CircuitOp>().addPass(om::createVerifyObjectFieldsPass());
293
294 // Check for static asserts.
295 pm.nest<firrtl::CircuitOp>().addPass(circt::firrtl::createLint(
296 {/*lintStaticAsserts=*/opt.getLintStaticAsserts(),
297 /*lintXmrsInDesign=*/opt.getLintXmrsInDesign()}));
298
300 opt.getVerificationFlavor()));
301
302 if (!opt.shouldDisableOptimization()) {
303 auto &modulePM = pm.nest<hw::HWModuleOp>();
304 modulePM.addPass(mlir::createCSEPass());
305 modulePM.addPass(createSimpleCanonicalizerPass());
306 }
307
308 // Check inner symbols and inner refs.
309 pm.addPass(hw::createVerifyInnerRefNamespace());
310
311 // Check OM object fields.
312 pm.addPass(om::createVerifyObjectFieldsPass());
313
314 // Run the verif op verification pass
315 pm.addNestedPass<hw::HWModuleOp>(verif::createVerifyClockedAssertLikePass());
316
317 return success();
318}
319
320LogicalResult firtool::populateHWToSV(mlir::PassManager &pm,
321 const FirtoolOptions &opt) {
322 pm.nestAny().addPass(verif::createStripContractsPass());
323 pm.addPass(verif::createLowerFormalToHWPass());
324 pm.addPass(
325 verif::createLowerSymbolicValuesPass({opt.getSymbolicValueLowering()}));
326
327 if (opt.shouldExtractTestCode())
328 pm.addPass(sv::createSVExtractTestCodePass(
332
333 pm.addPass(seq::createExternalizeClockGatePass(opt.getClockGateOptions()));
334 pm.addPass(circt::createLowerSimToSVPass());
336 {/*disableRegRandomization=*/!opt.isRandomEnabled(
337 FirtoolOptions::RandomKind::Reg),
338 /*disableMemRandomization=*/
339 !opt.isRandomEnabled(FirtoolOptions::RandomKind::Mem),
340 /*emitSeparateAlwaysBlocks=*/
342 pm.addNestedPass<hw::HWModuleOp>(createLowerVerifToSVPass());
343 pm.addPass(seq::createHWMemSimImplPass(
344 {/*disableMemRandomization=*/!opt.isRandomEnabled(
345 FirtoolOptions::RandomKind::Mem),
346 /*disableRegRandomization=*/
347 !opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg),
348 /*replSeqMem=*/opt.shouldReplaceSequentialMemories(),
349 /*readEnableMode=*/opt.shouldIgnoreReadEnableMemories()
350 ? seq::ReadEnableMode::Ignore
351 : seq::ReadEnableMode::Undefined,
352 /*addMuxPragmas=*/opt.shouldAddMuxPragmas(),
353 /*addVivadoRAMAddressConflictSynthesisBugWorkaround=*/
355
356 // If enabled, run the optimizer.
357 if (!opt.shouldDisableOptimization()) {
358 auto &modulePM = pm.nest<hw::HWModuleOp>();
359 modulePM.addPass(mlir::createCSEPass());
360 modulePM.addPass(createSimpleCanonicalizerPass());
361 modulePM.addPass(mlir::createCSEPass());
362 modulePM.addPass(sv::createHWCleanupPass(
363 /*mergeAlwaysBlocks=*/!opt.shouldEmitSeparateAlwaysBlocks()));
364 }
365
366 // Check inner symbols and inner refs.
367 pm.addPass(hw::createVerifyInnerRefNamespace());
368
369 // Check OM object fields.
370 pm.addPass(om::createVerifyObjectFieldsPass());
371
372 return success();
373}
374
375namespace detail {
376LogicalResult
378 const firtool::FirtoolOptions &opt) {
379
380 // Run the verif op verification pass
381 pm.addNestedPass<hw::HWModuleOp>(verif::createVerifyClockedAssertLikePass());
382
383 // Legalize unsupported operations within the modules.
385
386 // Tidy up the IR to improve verilog emission quality.
387 if (!opt.shouldDisableOptimization())
388 pm.nest<hw::HWModuleOp>().addPass(sv::createPrettifyVerilogPass());
389
390 if (opt.shouldStripFirDebugInfo())
391 pm.addPass(circt::createStripDebugInfoWithPredPass([](mlir::Location loc) {
392 if (auto fileLoc = dyn_cast<FileLineColLoc>(loc))
393 return fileLoc.getFilename().getValue().ends_with(".fir");
394 return false;
395 }));
396
397 if (opt.shouldStripDebugInfo())
399 [](mlir::Location loc) { return true; }));
400
401 // Emit module and testbench hierarchy JSON files.
404
405 // Check inner symbols and inner refs.
406 pm.addPass(hw::createVerifyInnerRefNamespace());
407
408 // Check OM object fields.
410
411 return success();
412}
413} // namespace detail
414
415LogicalResult
416firtool::populateExportVerilog(mlir::PassManager &pm, const FirtoolOptions &opt,
417 std::unique_ptr<llvm::raw_ostream> os) {
419 return failure();
420
421 pm.addPass(createExportVerilogPass(std::move(os)));
422 return success();
423}
424
425LogicalResult firtool::populateExportVerilog(mlir::PassManager &pm,
426 const FirtoolOptions &opt,
427 llvm::raw_ostream &os) {
429 return failure();
430
431 pm.addPass(createExportVerilogPass(os));
432 return success();
433}
434
435LogicalResult firtool::populateExportSplitVerilog(mlir::PassManager &pm,
436 const FirtoolOptions &opt,
437 llvm::StringRef directory) {
439 return failure();
440
441 pm.addPass(createExportSplitVerilogPass(directory));
442 return success();
443}
444
445LogicalResult firtool::populateFinalizeIR(mlir::PassManager &pm,
446 const FirtoolOptions &opt) {
447 pm.addPass(firrtl::createFinalizeIR());
448 pm.addPass(om::createFreezePathsPass());
449
450 return success();
451}
452
453LogicalResult firtool::populateHWToBTOR2(mlir::PassManager &pm,
454 const FirtoolOptions &opt,
455 llvm::raw_ostream &os) {
457 pm.addNestedPass<hw::HWModuleOp>(circt::verif::createPrepareForFormalPass());
458 pm.addPass(circt::hw::createFlattenModules());
459 pm.addPass(circt::createConvertHWToBTOR2Pass(os));
460 return success();
461}
462
463//===----------------------------------------------------------------------===//
464// FIRTOOL CommandLine Options
465//===----------------------------------------------------------------------===//
466
467namespace {
468/// This struct contains command line options that can be used to initialize
469/// various bits of a Firtool pipeline. This uses a struct wrapper to avoid the
470/// need for global command line options.
471struct FirtoolCmdOptions {
472 llvm::cl::opt<std::string> outputFilename{
473 "o",
474 llvm::cl::desc("Output filename, or directory for split output"),
475 llvm::cl::value_desc("filename"),
476 llvm::cl::init("-"),
477 };
478
479 llvm::cl::opt<bool> disableAnnotationsUnknown{
480 "disable-annotation-unknown",
481 llvm::cl::desc("Ignore unknown annotations when parsing"),
482 llvm::cl::init(false)};
483
484 llvm::cl::opt<bool> disableAnnotationsClassless{
485 "disable-annotation-classless",
486 llvm::cl::desc("Ignore annotations without a class when parsing"),
487 llvm::cl::init(false)};
488
489 llvm::cl::opt<bool> lowerAnnotationsNoRefTypePorts{
490 "lower-annotations-no-ref-type-ports",
491 llvm::cl::desc(
492 "Create real ports instead of ref type ports when resolving "
493 "wiring problems inside the LowerAnnotations pass"),
494 llvm::cl::init(false), llvm::cl::Hidden};
495
496 llvm::cl::opt<bool> allowAddingPortsOnPublic{
497 "allow-adding-ports-on-public-modules",
498 llvm::cl::desc("Allow adding ports to public modules"),
499 llvm::cl::init(false), llvm::cl::Hidden};
500
501 llvm::cl::opt<bool> probesToSignals{
502 "probes-to-signals",
503 llvm::cl::desc("Convert probes to non-probe signals"),
504 llvm::cl::init(false), llvm::cl::Hidden};
505
507 preserveAggregate{
508 "preserve-aggregate",
509 llvm::cl::desc("Specify input file format:"),
510 llvm::cl::values(
512 "Preserve no aggregate"),
514 "Preserve only 1d vectors of ground type"),
516 "Preserve only vectors"),
518 "Preserve vectors and bundles")),
520 };
521
523 "preserve-values",
524 llvm::cl::desc("Specify the values which can be optimized away"),
525 llvm::cl::values(
526 clEnumValN(firrtl::PreserveValues::Strip, "strip",
527 "Strip all names. No name is preserved"),
528 clEnumValN(firrtl::PreserveValues::None, "none",
529 "Names could be preserved by best-effort unlike `strip`"),
530 clEnumValN(firrtl::PreserveValues::Named, "named",
531 "Preserve values with meaningful names"),
532 clEnumValN(firrtl::PreserveValues::All, "all",
533 "Preserve all values")),
534 llvm::cl::init(firrtl::PreserveValues::None)};
535
536 llvm::cl::opt<bool> enableDebugInfo{
537 "g", llvm::cl::desc("Enable the generation of debug information"),
538 llvm::cl::init(false)};
539
540 // Build mode options.
542 "O", llvm::cl::desc("Controls how much optimization should be performed"),
543 llvm::cl::values(clEnumValN(firtool::FirtoolOptions::BuildModeDebug,
544 "debug",
545 "Compile with only necessary optimizations"),
547 "release", "Compile with optimizations")),
549
550 llvm::cl::opt<bool> disableLayerSink{"disable-layer-sink",
551 llvm::cl::desc("Disable layer sink"),
552 cl::init(false)};
553
554 llvm::cl::opt<bool> disableOptimization{
555 "disable-opt",
556 llvm::cl::desc("Disable optimizations"),
557 };
558
559 llvm::cl::opt<bool> exportChiselInterface{
560 "export-chisel-interface",
561 llvm::cl::desc("Generate a Scala Chisel interface to the top level "
562 "module of the firrtl circuit"),
563 llvm::cl::init(false)};
564
565 llvm::cl::opt<std::string> chiselInterfaceOutDirectory{
566 "chisel-interface-out-dir",
567 llvm::cl::desc(
568 "The output directory for generated Chisel interface files"),
569 llvm::cl::init("")};
570
571 llvm::cl::opt<bool> vbToBV{
572 "vb-to-bv",
573 llvm::cl::desc("Transform vectors of bundles to bundles of vectors"),
574 llvm::cl::init(false)};
575
576 llvm::cl::opt<bool> noDedup{
577 "no-dedup",
578 llvm::cl::desc("Disable deduplication of structurally identical modules"),
579 llvm::cl::init(false)};
580
582 "grand-central-companion-mode",
583 llvm::cl::desc("Specifies the handling of Grand Central companions"),
584 ::llvm::cl::values(
585 clEnumValN(firrtl::CompanionMode::Bind, "bind",
586 "Lower companion instances to SystemVerilog binds"),
587 clEnumValN(firrtl::CompanionMode::Instantiate, "instantiate",
588 "Instantiate companions in the design"),
589 clEnumValN(firrtl::CompanionMode::Drop, "drop",
590 "Remove companions from the design")),
591 llvm::cl::init(firrtl::CompanionMode::Bind),
592 llvm::cl::Hidden,
593 };
594
595 llvm::cl::opt<bool> disableAggressiveMergeConnections{
596 "disable-aggressive-merge-connections",
597 llvm::cl::desc(
598 "Disable aggressive merge connections (i.e. merge all field-level "
599 "connections into bulk connections)"),
600 llvm::cl::init(false)};
601
602 llvm::cl::opt<bool> lowerMemories{
603 "lower-memories",
604 llvm::cl::desc("Lower memories to have memories with masks as an "
605 "array with one memory per ground type"),
606 llvm::cl::init(false)};
607
608 llvm::cl::opt<std::string> blackBoxRootPath{
609 "blackbox-path",
610 llvm::cl::desc(
611 "Optional path to use as the root of black box annotations"),
612 llvm::cl::value_desc("path"),
613 llvm::cl::init(""),
614 };
615
616 llvm::cl::opt<bool> replSeqMem{
617 "repl-seq-mem",
618 llvm::cl::desc("Replace the seq mem for macro replacement and emit "
619 "relevant metadata"),
620 llvm::cl::init(false)};
621
622 llvm::cl::opt<std::string> replSeqMemFile{
623 "repl-seq-mem-file", llvm::cl::desc("File name for seq mem metadata"),
624 llvm::cl::init("")};
625
626 llvm::cl::opt<bool> extractTestCode{
627 "extract-test-code", llvm::cl::desc("Run the extract test code pass"),
628 llvm::cl::init(false)};
629
630 llvm::cl::opt<bool> ignoreReadEnableMem{
631 "ignore-read-enable-mem",
632 llvm::cl::desc("Ignore the read enable signal, instead of "
633 "assigning X on read disable"),
634 llvm::cl::init(false)};
635
637 llvm::cl::desc(
638 "Disable random initialization code (may break semantics!)"),
639 llvm::cl::values(
640 clEnumValN(firtool::FirtoolOptions::RandomKind::Mem,
641 "disable-mem-randomization",
642 "Disable emission of memory randomization code"),
643 clEnumValN(firtool::FirtoolOptions::RandomKind::Reg,
644 "disable-reg-randomization",
645 "Disable emission of register randomization code"),
646 clEnumValN(firtool::FirtoolOptions::RandomKind::All,
647 "disable-all-randomization",
648 "Disable emission of all randomization code")),
649 llvm::cl::init(firtool::FirtoolOptions::RandomKind::None)};
650
651 llvm::cl::opt<std::string> outputAnnotationFilename{
652 "output-annotation-file",
653 llvm::cl::desc("Optional output annotation file"),
654 llvm::cl::CommaSeparated, llvm::cl::value_desc("filename")};
655
656 llvm::cl::opt<bool> enableAnnotationWarning{
657 "warn-on-unprocessed-annotations",
658 llvm::cl::desc(
659 "Warn about annotations that were not removed by lower-to-hw"),
660 llvm::cl::init(false)};
661
662 llvm::cl::opt<bool> addMuxPragmas{
663 "add-mux-pragmas",
664 llvm::cl::desc("Annotate mux pragmas for memory array access"),
665 llvm::cl::init(false)};
666
668 "verification-flavor",
669 llvm::cl::desc("Specify a verification flavor used in LowerFIRRTLToHW"),
670 llvm::cl::values(
671 clEnumValN(firrtl::VerificationFlavor::None, "none",
672 "Use the flavor specified by the op"),
673 clEnumValN(firrtl::VerificationFlavor::IfElseFatal, "if-else-fatal",
674 "Use Use `if(cond) else $fatal(..)` format"),
675 clEnumValN(firrtl::VerificationFlavor::Immediate, "immediate",
676 "Use immediate verif statements"),
677 clEnumValN(firrtl::VerificationFlavor::SVA, "sva", "Use SVA")),
678 llvm::cl::init(firrtl::VerificationFlavor::None)};
679
680 llvm::cl::opt<bool> emitSeparateAlwaysBlocks{
681 "emit-separate-always-blocks",
682 llvm::cl::desc(
683 "Prevent always blocks from being merged and emit constructs into "
684 "separate always blocks whenever possible"),
685 llvm::cl::init(false)};
686
687 llvm::cl::opt<bool> etcDisableInstanceExtraction{
688 "etc-disable-instance-extraction",
689 llvm::cl::desc("Disable extracting instances only that feed test code"),
690 llvm::cl::init(false)};
691
692 llvm::cl::opt<bool> etcDisableRegisterExtraction{
693 "etc-disable-register-extraction",
694 llvm::cl::desc("Disable extracting registers that only feed test code"),
695 llvm::cl::init(false)};
696
697 llvm::cl::opt<bool> etcDisableModuleInlining{
698 "etc-disable-module-inlining",
699 llvm::cl::desc("Disable inlining modules that only feed test code"),
700 llvm::cl::init(false)};
701
702 llvm::cl::opt<bool> addVivadoRAMAddressConflictSynthesisBugWorkaround{
703 "add-vivado-ram-address-conflict-synthesis-bug-workaround",
704 llvm::cl::desc(
705 "Add a vivado specific SV attribute (* ram_style = "
706 "\"distributed\" *) to unpacked array registers as a workaronud "
707 "for a vivado synthesis bug that incorrectly modifies "
708 "address conflict behavivor of combinational memories"),
709 llvm::cl::init(false)};
710
711 //===----------------------------------------------------------------------===
712 // External Clock Gate Options
713 //===----------------------------------------------------------------------===
714
715 llvm::cl::opt<std::string> ckgModuleName{
716 "ckg-name", llvm::cl::desc("Clock gate module name"),
717 llvm::cl::init("EICG_wrapper")};
718
719 llvm::cl::opt<std::string> ckgInputName{
720 "ckg-input", llvm::cl::desc("Clock gate input port name"),
721 llvm::cl::init("in")};
722
723 llvm::cl::opt<std::string> ckgOutputName{
724 "ckg-output", llvm::cl::desc("Clock gate output port name"),
725 llvm::cl::init("out")};
726
727 llvm::cl::opt<std::string> ckgEnableName{
728 "ckg-enable", llvm::cl::desc("Clock gate enable port name"),
729 llvm::cl::init("en")};
730
731 llvm::cl::opt<std::string> ckgTestEnableName{
732 "ckg-test-enable",
733 llvm::cl::desc("Clock gate test enable port name (optional)"),
734 llvm::cl::init("test_en")};
735
736 llvm::cl::opt<bool> exportModuleHierarchy{
737 "export-module-hierarchy",
738 llvm::cl::desc("Export module and instance hierarchy as JSON"),
739 llvm::cl::init(false)};
740
741 llvm::cl::opt<bool> stripFirDebugInfo{
742 "strip-fir-debug-info",
743 llvm::cl::desc(
744 "Disable source fir locator information in output Verilog"),
745 llvm::cl::init(true)};
746
747 llvm::cl::opt<bool> stripDebugInfo{
748 "strip-debug-info",
749 llvm::cl::desc("Disable source locator information in output Verilog"),
750 llvm::cl::init(false)};
751
752 llvm::cl::opt<bool> fixupEICGWrapper{
753 "fixup-eicg-wrapper",
754 llvm::cl::desc("Lower `EICG_wrapper` modules into clock gate intrinsics"),
755 llvm::cl::init(false)};
756
757 llvm::cl::opt<bool> addCompanionAssume{
758 "add-companion-assume",
759 llvm::cl::desc("Add companion assumes to assertions"),
760 llvm::cl::init(false)};
761
762 llvm::cl::opt<bool> selectDefaultInstanceChoice{
763 "select-default-for-unspecified-instance-choice",
764 llvm::cl::desc(
765 "Specialize instance choice to default, if no option selected"),
766 llvm::cl::init(false)};
767
769 "symbolic-values",
770 llvm::cl::desc("Control how symbolic values are lowered"),
771 llvm::cl::init(verif::SymbolicValueLowering::ExtModule),
772 verif::symbolicValueLoweringCLValues()};
773
774 llvm::cl::opt<bool> disableWireElimination{
775 "disable-wire-elimination", llvm::cl::desc("Disable wire elimination"),
776 llvm::cl::init(false)};
777
778 //===----------------------------------------------------------------------===
779 // Lint options
780 //===----------------------------------------------------------------------===
781
782 llvm::cl::opt<bool> lintStaticAsserts{
783 "lint-static-asserts", llvm::cl::desc("Lint static assertions"),
784 llvm::cl::init(true)};
785 // TODO: Change this default to 'true' once this has been better tested and
786 // `-sv-extract-test-code` has been removed.
787 llvm::cl::opt<bool> lintXmrsInDesign{
788 "lint-xmrs-in-design", llvm::cl::desc("Lint XMRs in the design"),
789 llvm::cl::init(false)};
790};
791} // namespace
792
793static llvm::ManagedStatic<FirtoolCmdOptions> clOptions;
794
795/// Register a set of useful command-line options that can be used to configure
796/// various flags within the MLIRContext. These flags are used when constructing
797/// an MLIR context for initialization.
799 // Make sure that the options struct has been initialized.
800 *clOptions;
801}
802
803// Initialize the firtool options with defaults supplied by the cl::opts above.
805 : outputFilename("-"), disableAnnotationsUnknown(false),
806 disableAnnotationsClassless(false), lowerAnnotationsNoRefTypePorts(false),
807 allowAddingPortsOnPublic(false), probesToSignals(false),
808 preserveAggregate(firrtl::PreserveAggregate::None),
809 preserveMode(firrtl::PreserveValues::None), enableDebugInfo(false),
810 buildMode(BuildModeRelease), disableLayerSink(false),
811 disableOptimization(false), exportChiselInterface(false),
812 chiselInterfaceOutDirectory(""), vbToBV(false), noDedup(false),
813 companionMode(firrtl::CompanionMode::Bind),
814 disableAggressiveMergeConnections(false), lowerMemories(false),
815 blackBoxRootPath(""), replSeqMem(false), replSeqMemFile(""),
816 extractTestCode(false), ignoreReadEnableMem(false),
817 disableRandom(RandomKind::None), outputAnnotationFilename(""),
818 enableAnnotationWarning(false), addMuxPragmas(false),
819 verificationFlavor(firrtl::VerificationFlavor::None),
820 emitSeparateAlwaysBlocks(false), etcDisableInstanceExtraction(false),
821 etcDisableRegisterExtraction(false), etcDisableModuleInlining(false),
822 addVivadoRAMAddressConflictSynthesisBugWorkaround(false),
823 ckgModuleName("EICG_wrapper"), ckgInputName("in"), ckgOutputName("out"),
824 ckgEnableName("en"), ckgTestEnableName("test_en"), ckgInstName("ckg"),
825 exportModuleHierarchy(false), stripFirDebugInfo(true),
826 stripDebugInfo(false), fixupEICGWrapper(false), addCompanionAssume(false),
827 disableCSEinClasses(false), selectDefaultInstanceChoice(false),
828 symbolicValueLowering(verif::SymbolicValueLowering::ExtModule),
829 disableWireElimination(false), lintStaticAsserts(true),
830 lintXmrsInDesign(true) {
831 if (!clOptions.isConstructed())
832 return;
833 outputFilename = clOptions->outputFilename;
834 disableAnnotationsUnknown = clOptions->disableAnnotationsUnknown;
835 disableAnnotationsClassless = clOptions->disableAnnotationsClassless;
836 lowerAnnotationsNoRefTypePorts = clOptions->lowerAnnotationsNoRefTypePorts;
837 allowAddingPortsOnPublic = clOptions->allowAddingPortsOnPublic;
838 probesToSignals = clOptions->probesToSignals;
839 preserveAggregate = clOptions->preserveAggregate;
840 preserveMode = clOptions->preserveMode;
841 enableDebugInfo = clOptions->enableDebugInfo;
842 buildMode = clOptions->buildMode;
843 disableLayerSink = clOptions->disableLayerSink;
844 disableOptimization = clOptions->disableOptimization;
845 exportChiselInterface = clOptions->exportChiselInterface;
846 chiselInterfaceOutDirectory = clOptions->chiselInterfaceOutDirectory;
847 vbToBV = clOptions->vbToBV;
848 noDedup = clOptions->noDedup;
849 companionMode = clOptions->companionMode;
851 clOptions->disableAggressiveMergeConnections;
852 lowerMemories = clOptions->lowerMemories;
853 blackBoxRootPath = clOptions->blackBoxRootPath;
854 replSeqMem = clOptions->replSeqMem;
855 replSeqMemFile = clOptions->replSeqMemFile;
856 extractTestCode = clOptions->extractTestCode;
857 ignoreReadEnableMem = clOptions->ignoreReadEnableMem;
858 disableRandom = clOptions->disableRandom;
859 outputAnnotationFilename = clOptions->outputAnnotationFilename;
860 enableAnnotationWarning = clOptions->enableAnnotationWarning;
861 addMuxPragmas = clOptions->addMuxPragmas;
862 verificationFlavor = clOptions->verificationFlavor;
863 emitSeparateAlwaysBlocks = clOptions->emitSeparateAlwaysBlocks;
864 etcDisableInstanceExtraction = clOptions->etcDisableInstanceExtraction;
865 etcDisableRegisterExtraction = clOptions->etcDisableRegisterExtraction;
866 etcDisableModuleInlining = clOptions->etcDisableModuleInlining;
868 clOptions->addVivadoRAMAddressConflictSynthesisBugWorkaround;
869 ckgModuleName = clOptions->ckgModuleName;
870 ckgInputName = clOptions->ckgInputName;
871 ckgOutputName = clOptions->ckgOutputName;
872 ckgEnableName = clOptions->ckgEnableName;
873 ckgTestEnableName = clOptions->ckgTestEnableName;
874 exportModuleHierarchy = clOptions->exportModuleHierarchy;
875 stripFirDebugInfo = clOptions->stripFirDebugInfo;
876 stripDebugInfo = clOptions->stripDebugInfo;
877 fixupEICGWrapper = clOptions->fixupEICGWrapper;
878 addCompanionAssume = clOptions->addCompanionAssume;
879 selectDefaultInstanceChoice = clOptions->selectDefaultInstanceChoice;
880 symbolicValueLowering = clOptions->symbolicValueLowering;
881 disableWireElimination = clOptions->disableWireElimination;
882 lintStaticAsserts = clOptions->lintStaticAsserts;
883 lintXmrsInDesign = clOptions->lintXmrsInDesign;
884}
static LogicalResult exportChiselInterface(CircuitOp circuit, llvm::raw_ostream &os)
Exports a Chisel interface to the output stream.
static llvm::ManagedStatic< FirtoolCmdOptions > clOptions
Definition Firtool.cpp:793
Set of options used to control the behavior of the firtool pipeline.
Definition Firtool.h:31
bool shouldStripDebugInfo() const
Definition Firtool.h:117
firrtl::PreserveAggregate::PreserveMode getPreserveAggregate() const
Definition Firtool.h:65
bool shouldAddVivadoRAMAddressConflictSynthesisBugWorkaround() const
Definition Firtool.h:129
bool shouldDisableLayerSink() const
Definition Firtool.h:100
firrtl::PreserveValues::PreserveMode preserveMode
Definition Firtool.h:414
bool shouldAddCompanionAssume() const
Definition Firtool.h:134
auto getVerificationFlavor() const
Definition Firtool.h:124
bool isDefaultOutputFilename() const
Definition Firtool.h:85
StringRef getOutputFilename() const
Definition Firtool.h:55
bool shouldDisableAggressiveMergeConnections() const
Definition Firtool.h:120
StringRef getReplaceSequentialMemoriesFile() const
Definition Firtool.h:60
bool addVivadoRAMAddressConflictSynthesisBugWorkaround
Definition Firtool.h:440
bool shouldExportChiselInterface() const
Definition Firtool.h:106
bool shouldExtractTestCode() const
Definition Firtool.h:132
std::string chiselInterfaceOutDirectory
Definition Firtool.h:420
bool shouldFixupEICGWrapper() const
Definition Firtool.h:133
bool shouldConvertProbesToSignals() const
Definition Firtool.h:98
firrtl::PreserveValues::PreserveMode getPreserveMode() const
Definition Firtool.h:43
StringRef getBlackBoxRootPath() const
Definition Firtool.h:56
bool shouldDisableCSEinClasses() const
Definition Firtool.h:135
bool shouldDisableOptimization() const
Definition Firtool.h:101
firrtl::CompanionMode getCompanionMode() const
Definition Firtool.h:68
bool shouldDisableClasslessAnnotations() const
Definition Firtool.h:89
bool shouldReplaceSequentialMemories() const
Definition Firtool.h:99
bool shouldIgnoreReadEnableMemories() const
Definition Firtool.h:105
bool isRandomEnabled(RandomKind kind) const
Definition Firtool.h:39
bool shouldDisableUnknownAnnotations() const
Definition Firtool.h:86
bool shouldAddMuxPragmas() const
Definition Firtool.h:128
bool shouldEnableAnnotationWarning() const
Definition Firtool.h:123
bool shouldEtcDisableInstanceExtraction() const
Definition Firtool.h:108
bool shouldConvertVecOfBundle() const
Definition Firtool.h:107
StringRef getOutputAnnotationFilename() const
Definition Firtool.h:61
bool shouldStripFirDebugInfo() const
Definition Firtool.h:118
bool shouldEtcDisableRegisterExtraction() const
Definition Firtool.h:111
std::string outputAnnotationFilename
Definition Firtool.h:432
firrtl::VerificationFlavor verificationFlavor
Definition Firtool.h:435
firrtl::PreserveAggregate::PreserveMode preserveAggregate
Definition Firtool.h:413
bool shouldLowerMemories() const
Definition Firtool.h:102
bool shouldEtcDisableModuleInlining() const
Definition Firtool.h:114
bool shouldAllowAddingPortsOnPublic() const
Definition Firtool.h:95
bool getLintStaticAsserts() const
Definition Firtool.h:145
bool shouldLowerNoRefTypePortAnnotations() const
Definition Firtool.h:92
verif::SymbolicValueLowering getSymbolicValueLowering() const
Definition Firtool.h:140
bool shouldExportModuleHierarchy() const
Definition Firtool.h:119
firrtl::CompanionMode companionMode
Definition Firtool.h:423
bool shouldDisableWireElimination() const
Definition Firtool.h:143
bool shouldSelectDefaultInstanceChoice() const
Definition Firtool.h:136
verif::SymbolicValueLowering symbolicValueLowering
Definition Firtool.h:454
bool getLintXmrsInDesign() const
Definition Firtool.h:147
seq::ExternalizeClockGateOptions getClockGateOptions() const
Definition Firtool.h:70
bool shouldEnableDebugInfo() const
Definition Firtool.h:104
bool shouldEmitSeparateAlwaysBlocks() const
Definition Firtool.h:125
StringRef getChiselInterfaceOutputDirectory() const
Definition Firtool.h:57
@ All
Preserve all aggregate values.
Definition Passes.h:40
@ OneDimVec
Preserve only 1d vectors of ground type (e.g. UInt<2>[3]).
Definition Passes.h:34
@ Vec
Preserve only vectors (e.g. UInt<2>[3][3]).
Definition Passes.h:37
@ None
Don't preserve aggregate at all.
Definition Passes.h:31
@ None
Don't explicitly preserve any named values.
Definition Passes.h:52
@ Strip
Strip all names. No name on declaration is preserved.
Definition Passes.h:48
LogicalResult populateLowFIRRTLToHW(mlir::PassManager &pm, const FirtoolOptions &opt, StringRef inputFilename)
Definition Firtool.cpp:236
LogicalResult populateHWToBTOR2(mlir::PassManager &pm, const FirtoolOptions &opt, llvm::raw_ostream &os)
Definition Firtool.cpp:453
LogicalResult populateExportSplitVerilog(mlir::PassManager &pm, const FirtoolOptions &opt, llvm::StringRef directory)
Definition Firtool.cpp:435
LogicalResult populateHWToSV(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition Firtool.cpp:320
LogicalResult populateExportVerilog(mlir::PassManager &pm, const FirtoolOptions &opt, std::unique_ptr< llvm::raw_ostream > os)
Definition Firtool.cpp:416
LogicalResult populatePreprocessTransforms(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition Firtool.cpp:27
void registerFirtoolCLOptions()
Register a set of useful command-line options that can be used to configure various flags within the ...
Definition Firtool.cpp:798
LogicalResult populateFinalizeIR(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition Firtool.cpp:445
LogicalResult populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition Firtool.cpp:55
std::unique_ptr< mlir::Pass > createVerifyObjectFieldsPass()
std::unique_ptr< mlir::Pass > createHWExportModuleHierarchyPass()
std::unique_ptr< mlir::Pass > createHWLegalizeModulesPass()
std::unique_ptr< mlir::Pass > createPrettifyVerilogPass()
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< mlir::Pass > createExportSplitChiselInterfacePass(mlir::StringRef outputDirectory="./")
std::unique_ptr< OperationPass< hw::HWModuleOp > > createLowerVerifToSVPass()
Create the Verif to SV conversion pass.
std::unique_ptr< mlir::Pass > createLowerSeqToSVPass(const LowerSeqToSVOptions &options={})
Definition SeqToSV.cpp:858
std::unique_ptr< mlir::Pass > createLowerLTLToCorePass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLToHWPass(bool enableAnnotationWarning=false, firrtl::VerificationFlavor assertionFlavor=firrtl::VerificationFlavor::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
Definition SimToSV.cpp:379
std::unique_ptr< Pass > createSimpleCanonicalizerPass()
Create a simple canonicalizer pass.
Definition Passes.cpp:15
std::unique_ptr< mlir::Pass > createConvertHWToBTOR2Pass()
std::unique_ptr< mlir::Pass > createExportChiselInterfacePass()
std::unique_ptr< mlir::Pass > createExportVerilogPass()
std::unique_ptr< mlir::Pass > createStripDebugInfoWithPredPass(const std::function< bool(mlir::Location)> &pred)
Creates a pass to strip debug information from a function.
LogicalResult populatePrepareForExportVerilog(mlir::PassManager &pm, const firtool::FirtoolOptions &opt)
Definition Firtool.cpp:377
Definition verif.py:1