20#include "mlir/Transforms/Passes.h"
21#include "llvm/Support/FileSystem.h"
22#include "llvm/Support/Path.h"
29 pm.nest<firrtl::CircuitOp>().addPass(
30 firrtl::createCheckRecursiveInstantiation());
31 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createCheckLayers());
33 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerOpenAggs());
35 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createResolvePaths());
37 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerFIRRTLAnnotations(
44 pm.nest<firrtl::CircuitOp>().addNestedPass<firrtl::FModuleOp>(
45 firrtl::createMaterializeDebugInfo());
47 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerIntmodules(
49 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
50 firrtl::createLowerIntrinsics());
59 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createSpecializeOption(
62 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerSignatures());
68 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInjectDUTHierarchy());
72 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
73 mlir::createCSEPass());
75 pm.nest<firrtl::CircuitOp>().nestAny().addPass(mlir::createCSEPass());
78 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
79 firrtl::createPassiveWires());
81 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
84 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
85 firrtl::createLowerCHIRRTLPass());
89 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
90 firrtl::createLowerMatches());
93 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferWidths());
95 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createMemToRegOfVec(
99 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferResets());
108 pm.nest<firrtl::CircuitOp>().addPass(
113 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDropConst());
116 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDedup());
119 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypes(
122 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createVBToBV());
126 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
127 firrtl::createFlattenMemory());
132 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypes(
137 auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
138 modulePM.addPass(firrtl::createExpandWhens());
139 modulePM.addPass(firrtl::createSFCCompat());
142 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createCheckCombLoops());
146 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createSpecializeLayers());
150 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createProbesToSignals());
152 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInliner());
154 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
155 firrtl::createLayerMerge());
162 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
163 firrtl::createRandomizeRegisterInit());
167 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
173 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
174 firrtl::createInferReadWrite());
177 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerMemory());
180 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
181 circt::firrtl::createCreateCompanionAssume());
184 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstProp());
186 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createAddSeqMemPorts());
188 pm.addPass(firrtl::createCreateSiFiveMetadata(
195 pm.addNestedPass<firrtl::CircuitOp>(firrtl::createExtractInstances());
199 pm.addNestedPass<firrtl::CircuitOp>(mlir::createSymbolDCEPass());
202 pm.addPass(firrtl::createInnerSymbolDCE());
209 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
210 circt::firrtl::createEliminateWires());
211 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
213 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
214 circt::firrtl::createRegisterOptimizer());
217 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstProp());
218 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
220 pm.addPass(firrtl::createIMDeadCodeElim());
224 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
225 firrtl::createMergeConnections(
230 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
231 firrtl::createVectorization());
238 StringRef inputFilename) {
243 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLayerSink());
248 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerXMR());
257 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerLayers());
259 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
263 if (outputFilename ==
"-")
266 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createAssignOutputDirs(
267 {outputFilename.str()}));
275 pm.addNestedPass<firrtl::CircuitOp>(
280 ? llvm::sys::path::parent_path(inputFilename)
282 pm.nest<firrtl::CircuitOp>().addPass(
283 firrtl::createBlackBoxReader({blackBoxRoot.str()}));
287 pm.nest<firrtl::CircuitOp>().addPass(
290 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerDPI());
291 pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerClasses());
292 pm.nest<firrtl::CircuitOp>().addPass(om::createVerifyObjectFieldsPass());
295 pm.nest<firrtl::CircuitOp>().addPass(circt::firrtl::createLint(
304 modulePM.addPass(mlir::createCSEPass());
309 pm.addPass(hw::createVerifyInnerRefNamespace());
312 pm.addPass(om::createVerifyObjectFieldsPass());
315 pm.addNestedPass<
hw::HWModuleOp>(verif::createVerifyClockedAssertLikePass());
322 pm.nestAny().addPass(verif::createStripContractsPass());
323 pm.addPass(verif::createLowerFormalToHWPass());
328 pm.addPass(sv::createSVExtractTestCodePass(
337 FirtoolOptions::RandomKind::Reg),
343 pm.addPass(seq::createHWMemSimImplPass(
345 FirtoolOptions::RandomKind::Mem),
350 ? seq::ReadEnableMode::Ignore
351 : seq::ReadEnableMode::Undefined,
359 modulePM.addPass(mlir::createCSEPass());
361 modulePM.addPass(mlir::createCSEPass());
362 modulePM.addPass(sv::createHWCleanupPass(
367 pm.addPass(hw::createVerifyInnerRefNamespace());
370 pm.addPass(om::createVerifyObjectFieldsPass());
381 pm.addNestedPass<
hw::HWModuleOp>(verif::createVerifyClockedAssertLikePass());
392 if (
auto fileLoc = dyn_cast<FileLineColLoc>(loc))
393 return fileLoc.getFilename().getValue().ends_with(
".fir");
399 [](mlir::Location loc) {
return true; }));
406 pm.addPass(hw::createVerifyInnerRefNamespace());
417 std::unique_ptr<llvm::raw_ostream> os) {
427 llvm::raw_ostream &os) {
437 llvm::StringRef directory) {
447 pm.addPass(firrtl::createFinalizeIR());
448 pm.addPass(om::createFreezePathsPass());
455 llvm::raw_ostream &os) {
457 pm.addNestedPass<
hw::HWModuleOp>(circt::verif::createPrepareForFormalPass());
458 pm.addPass(circt::hw::createFlattenModules());
471struct FirtoolCmdOptions {
474 llvm::cl::desc(
"Output filename, or directory for split output"),
475 llvm::cl::value_desc(
"filename"),
480 "disable-annotation-unknown",
481 llvm::cl::desc(
"Ignore unknown annotations when parsing"),
482 llvm::cl::init(
false)};
485 "disable-annotation-classless",
486 llvm::cl::desc(
"Ignore annotations without a class when parsing"),
487 llvm::cl::init(
false)};
490 "lower-annotations-no-ref-type-ports",
492 "Create real ports instead of ref type ports when resolving "
493 "wiring problems inside the LowerAnnotations pass"),
494 llvm::cl::init(
false), llvm::cl::Hidden};
497 "allow-adding-ports-on-public-modules",
498 llvm::cl::desc(
"Allow adding ports to public modules"),
499 llvm::cl::init(
false), llvm::cl::Hidden};
503 llvm::cl::desc(
"Convert probes to non-probe signals"),
504 llvm::cl::init(
false), llvm::cl::Hidden};
508 "preserve-aggregate",
509 llvm::cl::desc(
"Specify input file format:"),
512 "Preserve no aggregate"),
514 "Preserve only 1d vectors of ground type"),
516 "Preserve only vectors"),
518 "Preserve vectors and bundles")),
524 llvm::cl::desc(
"Specify the values which can be optimized away"),
527 "Strip all names. No name is preserved"),
529 "Names could be preserved by best-effort unlike `strip`"),
531 "Preserve values with meaningful names"),
533 "Preserve all values")),
537 "g", llvm::cl::desc(
"Enable the generation of debug information"),
538 llvm::cl::init(
false)};
542 "O", llvm::cl::desc(
"Controls how much optimization should be performed"),
545 "Compile with only necessary optimizations"),
547 "release",
"Compile with optimizations")),
551 llvm::cl::desc(
"Disable layer sink"),
556 llvm::cl::desc(
"Disable optimizations"),
560 "export-chisel-interface",
561 llvm::cl::desc(
"Generate a Scala Chisel interface to the top level "
562 "module of the firrtl circuit"),
563 llvm::cl::init(
false)};
566 "chisel-interface-out-dir",
568 "The output directory for generated Chisel interface files"),
573 llvm::cl::desc(
"Transform vectors of bundles to bundles of vectors"),
574 llvm::cl::init(
false)};
578 llvm::cl::desc(
"Disable deduplication of structurally identical modules"),
579 llvm::cl::init(
false)};
582 "grand-central-companion-mode",
583 llvm::cl::desc(
"Specifies the handling of Grand Central companions"),
585 clEnumValN(firrtl::CompanionMode::Bind,
"bind",
586 "Lower companion instances to SystemVerilog binds"),
587 clEnumValN(firrtl::CompanionMode::Instantiate,
"instantiate",
588 "Instantiate companions in the design"),
589 clEnumValN(firrtl::CompanionMode::Drop,
"drop",
590 "Remove companions from the design")),
591 llvm::cl::init(firrtl::CompanionMode::Bind),
596 "disable-aggressive-merge-connections",
598 "Disable aggressive merge connections (i.e. merge all field-level "
599 "connections into bulk connections)"),
600 llvm::cl::init(
false)};
604 llvm::cl::desc(
"Lower memories to have memories with masks as an "
605 "array with one memory per ground type"),
606 llvm::cl::init(
false)};
611 "Optional path to use as the root of black box annotations"),
612 llvm::cl::value_desc(
"path"),
618 llvm::cl::desc(
"Replace the seq mem for macro replacement and emit "
619 "relevant metadata"),
620 llvm::cl::init(
false)};
623 "repl-seq-mem-file", llvm::cl::desc(
"File name for seq mem metadata"),
627 "extract-test-code", llvm::cl::desc(
"Run the extract test code pass"),
628 llvm::cl::init(
false)};
631 "ignore-read-enable-mem",
632 llvm::cl::desc(
"Ignore the read enable signal, instead of "
633 "assigning X on read disable"),
634 llvm::cl::init(
false)};
638 "Disable random initialization code (may break semantics!)"),
640 clEnumValN(firtool::FirtoolOptions::RandomKind::Mem,
641 "disable-mem-randomization",
642 "Disable emission of memory randomization code"),
643 clEnumValN(firtool::FirtoolOptions::RandomKind::Reg,
644 "disable-reg-randomization",
645 "Disable emission of register randomization code"),
646 clEnumValN(firtool::FirtoolOptions::RandomKind::All,
647 "disable-all-randomization",
648 "Disable emission of all randomization code")),
649 llvm::cl::init(firtool::FirtoolOptions::RandomKind::None)};
652 "output-annotation-file",
653 llvm::cl::desc(
"Optional output annotation file"),
654 llvm::cl::CommaSeparated, llvm::cl::value_desc(
"filename")};
657 "warn-on-unprocessed-annotations",
659 "Warn about annotations that were not removed by lower-to-hw"),
660 llvm::cl::init(
false)};
664 llvm::cl::desc(
"Annotate mux pragmas for memory array access"),
665 llvm::cl::init(
false)};
668 "verification-flavor",
669 llvm::cl::desc(
"Specify a verification flavor used in LowerFIRRTLToHW"),
671 clEnumValN(firrtl::VerificationFlavor::None,
"none",
672 "Use the flavor specified by the op"),
673 clEnumValN(firrtl::VerificationFlavor::IfElseFatal,
"if-else-fatal",
674 "Use Use `if(cond) else $fatal(..)` format"),
675 clEnumValN(firrtl::VerificationFlavor::Immediate,
"immediate",
676 "Use immediate verif statements"),
677 clEnumValN(firrtl::VerificationFlavor::SVA,
"sva",
"Use SVA")),
678 llvm::cl::init(firrtl::VerificationFlavor::None)};
681 "emit-separate-always-blocks",
683 "Prevent always blocks from being merged and emit constructs into "
684 "separate always blocks whenever possible"),
685 llvm::cl::init(
false)};
688 "etc-disable-instance-extraction",
689 llvm::cl::desc(
"Disable extracting instances only that feed test code"),
690 llvm::cl::init(
false)};
693 "etc-disable-register-extraction",
694 llvm::cl::desc(
"Disable extracting registers that only feed test code"),
695 llvm::cl::init(
false)};
698 "etc-disable-module-inlining",
699 llvm::cl::desc(
"Disable inlining modules that only feed test code"),
700 llvm::cl::init(
false)};
703 "add-vivado-ram-address-conflict-synthesis-bug-workaround",
705 "Add a vivado specific SV attribute (* ram_style = "
706 "\"distributed\" *) to unpacked array registers as a workaronud "
707 "for a vivado synthesis bug that incorrectly modifies "
708 "address conflict behavivor of combinational memories"),
709 llvm::cl::init(
false)};
716 "ckg-name", llvm::cl::desc(
"Clock gate module name"),
717 llvm::cl::init(
"EICG_wrapper")};
720 "ckg-input", llvm::cl::desc(
"Clock gate input port name"),
721 llvm::cl::init(
"in")};
724 "ckg-output", llvm::cl::desc(
"Clock gate output port name"),
725 llvm::cl::init(
"out")};
728 "ckg-enable", llvm::cl::desc(
"Clock gate enable port name"),
729 llvm::cl::init(
"en")};
733 llvm::cl::desc(
"Clock gate test enable port name (optional)"),
734 llvm::cl::init(
"test_en")};
737 "export-module-hierarchy",
738 llvm::cl::desc(
"Export module and instance hierarchy as JSON"),
739 llvm::cl::init(
false)};
742 "strip-fir-debug-info",
744 "Disable source fir locator information in output Verilog"),
745 llvm::cl::init(
true)};
749 llvm::cl::desc(
"Disable source locator information in output Verilog"),
750 llvm::cl::init(
false)};
753 "fixup-eicg-wrapper",
754 llvm::cl::desc(
"Lower `EICG_wrapper` modules into clock gate intrinsics"),
755 llvm::cl::init(
false)};
758 "add-companion-assume",
759 llvm::cl::desc(
"Add companion assumes to assertions"),
760 llvm::cl::init(
false)};
763 "select-default-for-unspecified-instance-choice",
765 "Specialize instance choice to default, if no option selected"),
766 llvm::cl::init(
false)};
770 llvm::cl::desc(
"Control how symbolic values are lowered"),
771 llvm::cl::init(verif::SymbolicValueLowering::ExtModule),
772 verif::symbolicValueLoweringCLValues()};
775 "disable-wire-elimination", llvm::cl::desc(
"Disable wire elimination"),
776 llvm::cl::init(
false)};
783 "lint-static-asserts", llvm::cl::desc(
"Lint static assertions"),
784 llvm::cl::init(
true)};
788 "lint-xmrs-in-design", llvm::cl::desc(
"Lint XMRs in the design"),
789 llvm::cl::init(
false)};
805 : outputFilename(
"-"), disableAnnotationsUnknown(false),
806 disableAnnotationsClassless(false), lowerAnnotationsNoRefTypePorts(false),
807 allowAddingPortsOnPublic(false), probesToSignals(false),
808 preserveAggregate(firrtl::PreserveAggregate::None),
809 preserveMode(firrtl::PreserveValues::None), enableDebugInfo(false),
810 buildMode(BuildModeRelease), disableLayerSink(false),
812 chiselInterfaceOutDirectory(
""), vbToBV(false), noDedup(false),
813 companionMode(firrtl::CompanionMode::Bind),
814 disableAggressiveMergeConnections(false), lowerMemories(false),
815 blackBoxRootPath(
""), replSeqMem(false), replSeqMemFile(
""),
816 extractTestCode(false), ignoreReadEnableMem(false),
817 disableRandom(
RandomKind::None), outputAnnotationFilename(
""),
818 enableAnnotationWarning(false), addMuxPragmas(false),
819 verificationFlavor(firrtl::VerificationFlavor::None),
820 emitSeparateAlwaysBlocks(false), etcDisableInstanceExtraction(false),
821 etcDisableRegisterExtraction(false), etcDisableModuleInlining(false),
822 addVivadoRAMAddressConflictSynthesisBugWorkaround(false),
823 ckgModuleName(
"EICG_wrapper"), ckgInputName(
"in"), ckgOutputName(
"out"),
824 ckgEnableName(
"en"), ckgTestEnableName(
"test_en"), ckgInstName(
"ckg"),
825 exportModuleHierarchy(false), stripFirDebugInfo(true),
826 stripDebugInfo(false), fixupEICGWrapper(false), addCompanionAssume(false),
827 disableCSEinClasses(false), selectDefaultInstanceChoice(false),
828 symbolicValueLowering(
verif::SymbolicValueLowering::ExtModule),
829 disableWireElimination(false), lintStaticAsserts(true),
830 lintXmrsInDesign(true) {
851 clOptions->disableAggressiveMergeConnections;
868 clOptions->addVivadoRAMAddressConflictSynthesisBugWorkaround;
static LogicalResult exportChiselInterface(CircuitOp circuit, llvm::raw_ostream &os)
Exports a Chisel interface to the output stream.
@ All
Preserve all aggregate values.
@ OneDimVec
Preserve only 1d vectors of ground type (e.g. UInt<2>[3]).
@ Vec
Preserve only vectors (e.g. UInt<2>[3][3]).
@ None
Don't preserve aggregate at all.
@ None
Don't explicitly preserve any named values.
@ Strip
Strip all names. No name on declaration is preserved.
std::unique_ptr< mlir::Pass > createVerifyObjectFieldsPass()
std::unique_ptr< mlir::Pass > createHWExportModuleHierarchyPass()
std::unique_ptr< mlir::Pass > createHWLegalizeModulesPass()
std::unique_ptr< mlir::Pass > createPrettifyVerilogPass()
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< mlir::Pass > createExportSplitChiselInterfacePass(mlir::StringRef outputDirectory="./")
std::unique_ptr< OperationPass< hw::HWModuleOp > > createLowerVerifToSVPass()
Create the Verif to SV conversion pass.
std::unique_ptr< mlir::Pass > createLowerSeqToSVPass(const LowerSeqToSVOptions &options={})
std::unique_ptr< mlir::Pass > createLowerLTLToCorePass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLToHWPass(bool enableAnnotationWarning=false, firrtl::VerificationFlavor assertionFlavor=firrtl::VerificationFlavor::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
std::unique_ptr< Pass > createSimpleCanonicalizerPass()
Create a simple canonicalizer pass.
std::unique_ptr< mlir::Pass > createConvertHWToBTOR2Pass()
std::unique_ptr< mlir::Pass > createExportChiselInterfacePass()
std::unique_ptr< mlir::Pass > createExportVerilogPass()
std::unique_ptr< mlir::Pass > createStripDebugInfoWithPredPass(const std::function< bool(mlir::Location)> &pred)
Creates a pass to strip debug information from a function.
LogicalResult populatePrepareForExportVerilog(mlir::PassManager &pm, const firtool::FirtoolOptions &opt)