CIRCT  19.0.0git
Firtool.cpp
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1 //===- Firtool.cpp - Definitions for the firtool pipeline setup -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
18 #include "circt/Support/Passes.h"
20 #include "mlir/Transforms/Passes.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/Path.h"
23 
24 using namespace llvm;
25 using namespace circt;
26 
27 LogicalResult firtool::populatePreprocessTransforms(mlir::PassManager &pm,
28  const FirtoolOptions &opt) {
29  // Legalize away "open" aggregates to hw-only versions.
30  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerOpenAggsPass());
31 
32  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createResolvePathsPass());
33 
34  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerFIRRTLAnnotationsPass(
39 
40  if (opt.shouldEnableDebugInfo())
41  pm.nest<firrtl::CircuitOp>().addNestedPass<firrtl::FModuleOp>(
43 
44  pm.nest<firrtl::CircuitOp>().addPass(
46  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
48 
49  return success();
50 }
51 
52 LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
53  const FirtoolOptions &opt,
54  StringRef inputFilename) {
55  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerSignaturesPass());
56 
57  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInjectDUTHierarchyPass());
58 
59  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
61 
62  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
64 
65  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
67 
68  if (!opt.shouldDisableOptimization())
69  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
70  mlir::createCSEPass());
71 
72  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
74 
75  // Run LowerMatches before InferWidths, as the latter does not support the
76  // match statement, but it does support what they lower to.
77  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
79 
80  // Width inference creates canonicalization opportunities.
81  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferWidthsPass());
82 
83  pm.nest<firrtl::CircuitOp>().addPass(
86 
87  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferResetsPass());
88 
89  if (opt.shouldExportChiselInterface()) {
90  StringRef outdir = opt.getChiselInterfaceOutputDirectory();
91  if (opt.isDefaultOutputFilename() && outdir.empty()) {
92  pm.nest<firrtl::CircuitOp>().addPass(createExportChiselInterfacePass());
93  } else {
94  if (outdir.empty())
95  outdir = opt.getOutputFilename();
96  pm.nest<firrtl::CircuitOp>().addPass(
98  }
99  }
100 
101  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDropConstPass());
102 
103  if (opt.shouldDedup())
104  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createDedupPass());
105 
106  if (opt.shouldConvertVecOfBundle()) {
107  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypesPass(
109  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createVBToBVPass());
110  }
111 
112  if (!opt.shouldLowerMemories())
113  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
115 
116  // The input mlir file could be firrtl dialect so we might need to clean
117  // things up.
118  // pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerSignaturesPass());
119  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createLowerFIRRTLTypesPass(
120  opt.getPreserveAggregate(), firrtl::PreserveAggregate::None));
121 
122  {
123  auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
124  modulePM.addPass(firrtl::createExpandWhensPass());
125  modulePM.addPass(firrtl::createEliminateWiresPass());
126  modulePM.addPass(firrtl::createSFCCompatPass());
127  }
128 
129  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createCheckCombLoopsPass());
130 
131  // Must run this pass after all diagnostic passes have run, otherwise it can
132  // hide errors.
133  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createSpecializeLayersPass());
134 
135  {
136  auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
137  modulePM.addPass(firrtl::createLayerMergePass());
138  modulePM.addPass(firrtl::createLayerSinkPass());
139  }
140 
141  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerLayersPass());
142 
143  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInlinerPass());
144 
145  // Preset the random initialization parameters for each module. The current
146  // implementation assumes it can run at a time where every register is
147  // currently in the final module it will be emitted in, all registers have
148  // been created, and no registers have yet been removed.
149  if (opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg))
150  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
152 
153  // If we parsed a FIRRTL file and have optimizations enabled, clean it up.
154  if (!opt.shouldDisableOptimization())
155  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
157 
158  // Run the infer-rw pass, which merges read and write ports of a memory with
159  // mutually exclusive enables.
160  if (!opt.shouldDisableOptimization())
161  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
163 
165  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerMemoryPass());
166 
167  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createPrefixModulesPass());
168 
169  if (opt.shouldAddCompanionAssume())
170  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
172 
173  if (!opt.shouldDisableOptimization())
174  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstPropPass());
175 
176  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createAddSeqMemPortsPass());
177 
181 
182  pm.addNestedPass<firrtl::CircuitOp>(firrtl::createExtractInstancesPass());
183 
184  // Run passes to resolve Grand Central features. This should run before
185  // BlackBoxReader because Grand Central needs to inform BlackBoxReader where
186  // certain black boxes should be placed. Note: all Grand Central Taps related
187  // collateral is resolved entirely by LowerAnnotations.
188  pm.addNestedPass<firrtl::CircuitOp>(
190 
191  // Read black box source files into the IR.
192  StringRef blackBoxRoot = opt.getBlackBoxRootPath().empty()
193  ? llvm::sys::path::parent_path(inputFilename)
194  : opt.getBlackBoxRootPath();
195  pm.nest<firrtl::CircuitOp>().addPass(
196  firrtl::createBlackBoxReaderPass(blackBoxRoot));
197 
198  // Run SymbolDCE as late as possible, but before InnerSymbolDCE. This is for
199  // hierpathop's and just for general cleanup.
200  pm.addNestedPass<firrtl::CircuitOp>(mlir::createSymbolDCEPass());
201 
202  // Run InnerSymbolDCE as late as possible, but before IMDCE.
203  pm.addPass(firrtl::createInnerSymbolDCEPass());
204 
205  // The above passes, IMConstProp in particular, introduce additional
206  // canonicalization opportunities that we should pick up here before we
207  // proceed to output-specific pipelines.
208  if (!opt.shouldDisableOptimization()) {
209  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
211  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
213  // Re-run IMConstProp to propagate constants produced by register
214  // optimizations.
215  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createIMConstPropPass());
216  pm.addPass(firrtl::createIMDeadCodeElimPass());
217  }
218 
219  if (opt.shouldEmitOMIR())
220  pm.nest<firrtl::CircuitOp>().addPass(
222 
223  // Always run this, required for legalization.
224  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
227 
228  if (!opt.shouldDisableOptimization())
229  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
231 
232  auto outputFilename = opt.getOutputFilename();
233  if (outputFilename == "-")
234  outputFilename = "";
235 
236  pm.nest<firrtl::CircuitOp>().addPass(
237  firrtl::createAssignOutputDirsPass(outputFilename));
238  return success();
239 }
240 
241 LogicalResult firtool::populateLowFIRRTLToHW(mlir::PassManager &pm,
242  const FirtoolOptions &opt) {
243  // Remove TraceAnnotations and write their updated paths to an output
244  // annotation file.
245  pm.nest<firrtl::CircuitOp>().addPass(
247 
248  // Lower the ref.resolve and ref.send ops and remove the RefType ports.
249  // LowerToHW cannot handle RefType so, this pass must be run to remove all
250  // RefType ports and ops.
251  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerXMRPass());
252 
253  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerDPIPass());
254  pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerClassesPass());
255  pm.nest<firrtl::CircuitOp>().addPass(om::createVerifyObjectFieldsPass());
256 
257  // Check for static asserts.
258  pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
260 
262  opt.getVerificationFlavor()));
263 
264  if (!opt.shouldDisableOptimization()) {
265  auto &modulePM = pm.nest<hw::HWModuleOp>();
266  modulePM.addPass(mlir::createCSEPass());
267  modulePM.addPass(createSimpleCanonicalizerPass());
268  }
269 
270  // Check inner symbols and inner refs.
272 
273  // Check OM object fields.
274  pm.addPass(om::createVerifyObjectFieldsPass());
275 
276  // Run the verif op verification pass
278 
279  return success();
280 }
281 
282 LogicalResult firtool::populateHWToSV(mlir::PassManager &pm,
283  const FirtoolOptions &opt) {
284 
285  if (opt.shouldExtractTestCode())
290 
292  pm.addPass(circt::createLowerSimToSVPass());
294  {/*disableRegRandomization=*/!opt.isRandomEnabled(
295  FirtoolOptions::RandomKind::Reg),
296  /*disableMemRandomization=*/
297  !opt.isRandomEnabled(FirtoolOptions::RandomKind::Mem),
298  /*emitSeparateAlwaysBlocks=*/
300  pm.addNestedPass<hw::HWModuleOp>(createLowerVerifToSVPass());
301  pm.addPass(seq::createHWMemSimImplPass(
302  {/*disableMemRandomization=*/!opt.isRandomEnabled(
303  FirtoolOptions::RandomKind::Mem),
304  /*disableRegRandomization=*/
305  !opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg),
306  /*replSeqMem=*/opt.shouldReplicateSequentialMemories(),
307  /*readEnableMode=*/opt.shouldIgnoreReadEnableMemories()
308  ? seq::ReadEnableMode::Ignore
309  : seq::ReadEnableMode::Undefined,
310  /*addMuxPragmas=*/opt.shouldAddMuxPragmas(),
311  /*addVivadoRAMAddressConflictSynthesisBugWorkaround=*/
313 
314  // If enabled, run the optimizer.
315  if (!opt.shouldDisableOptimization()) {
316  auto &modulePM = pm.nest<hw::HWModuleOp>();
317  modulePM.addPass(mlir::createCSEPass());
318  modulePM.addPass(createSimpleCanonicalizerPass());
319  modulePM.addPass(mlir::createCSEPass());
320  modulePM.addPass(sv::createHWCleanupPass(
321  /*mergeAlwaysBlocks=*/!opt.shouldEmitSeparateAlwaysBlocks()));
322  }
323 
324  // Check inner symbols and inner refs.
326 
327  // Check OM object fields.
328  pm.addPass(om::createVerifyObjectFieldsPass());
329 
330  return success();
331 }
332 
333 namespace detail {
334 LogicalResult
335 populatePrepareForExportVerilog(mlir::PassManager &pm,
336  const firtool::FirtoolOptions &opt) {
337 
338  // Run the verif op verification pass
340 
341  // Legalize unsupported operations within the modules.
342  pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModulesPass());
343 
344  // Tidy up the IR to improve verilog emission quality.
345  if (!opt.shouldDisableOptimization())
346  pm.nest<hw::HWModuleOp>().addPass(sv::createPrettifyVerilogPass());
347 
348  if (opt.shouldStripFirDebugInfo())
349  pm.addPass(circt::createStripDebugInfoWithPredPass([](mlir::Location loc) {
350  if (auto fileLoc = dyn_cast<FileLineColLoc>(loc))
351  return fileLoc.getFilename().getValue().ends_with(".fir");
352  return false;
353  }));
354 
355  if (opt.shouldStripDebugInfo())
357  [](mlir::Location loc) { return true; }));
358 
359  // Emit module and testbench hierarchy JSON files.
360  if (opt.shouldExportModuleHierarchy())
362 
363  // Check inner symbols and inner refs.
365 
366  // Check OM object fields.
367  pm.addPass(om::createVerifyObjectFieldsPass());
368 
369  return success();
370 }
371 } // namespace detail
372 
373 LogicalResult
374 firtool::populateExportVerilog(mlir::PassManager &pm, const FirtoolOptions &opt,
375  std::unique_ptr<llvm::raw_ostream> os) {
376  if (failed(::detail::populatePrepareForExportVerilog(pm, opt)))
377  return failure();
378 
379  pm.addPass(createExportVerilogPass(std::move(os)));
380  return success();
381 }
382 
383 LogicalResult firtool::populateExportVerilog(mlir::PassManager &pm,
384  const FirtoolOptions &opt,
385  llvm::raw_ostream &os) {
386  if (failed(::detail::populatePrepareForExportVerilog(pm, opt)))
387  return failure();
388 
389  pm.addPass(createExportVerilogPass(os));
390  return success();
391 }
392 
393 LogicalResult firtool::populateExportSplitVerilog(mlir::PassManager &pm,
394  const FirtoolOptions &opt,
395  llvm::StringRef directory) {
396  if (failed(::detail::populatePrepareForExportVerilog(pm, opt)))
397  return failure();
398 
399  pm.addPass(createExportSplitVerilogPass(directory));
400  return success();
401 }
402 
403 LogicalResult firtool::populateFinalizeIR(mlir::PassManager &pm,
404  const FirtoolOptions &opt) {
405  pm.addPass(firrtl::createFinalizeIRPass());
406  pm.addPass(om::createFreezePathsPass());
407 
408  return success();
409 }
410 
411 LogicalResult firtool::populateHWToBTOR2(mlir::PassManager &pm,
412  const FirtoolOptions &opt,
413  llvm::raw_ostream &os) {
414  pm.addNestedPass<hw::HWModuleOp>(circt::createLowerLTLToCorePass());
417  pm.addNestedPass<hw::HWModuleOp>(circt::createConvertHWToBTOR2Pass(os));
418  return success();
419 }
420 
421 //===----------------------------------------------------------------------===//
422 // FIRTOOL CommandLine Options
423 //===----------------------------------------------------------------------===//
424 
425 namespace {
426 /// This struct contains command line options that can be used to initialize
427 /// various bits of a Firtool pipeline. This uses a struct wrapper to avoid the
428 /// need for global command line options.
429 struct FirtoolCmdOptions {
430  llvm::cl::opt<std::string> outputFilename{
431  "o",
432  llvm::cl::desc("Output filename, or directory for split output"),
433  llvm::cl::value_desc("filename"),
434  llvm::cl::init("-"),
435  };
436 
437  llvm::cl::opt<bool> disableAnnotationsUnknown{
438  "disable-annotation-unknown",
439  llvm::cl::desc("Ignore unknown annotations when parsing"),
440  llvm::cl::init(false)};
441 
442  llvm::cl::opt<bool> disableAnnotationsClassless{
443  "disable-annotation-classless",
444  llvm::cl::desc("Ignore annotations without a class when parsing"),
445  llvm::cl::init(false)};
446 
447  llvm::cl::opt<bool> lowerAnnotationsNoRefTypePorts{
448  "lower-annotations-no-ref-type-ports",
449  llvm::cl::desc(
450  "Create real ports instead of ref type ports when resolving "
451  "wiring problems inside the LowerAnnotations pass"),
452  llvm::cl::init(false), llvm::cl::Hidden};
453 
454  llvm::cl::opt<bool> allowAddingPortsOnPublic{
455  "allow-adding-ports-on-public-modules",
456  llvm::cl::desc("Allow adding ports to public modules"),
457  llvm::cl::init(false), llvm::cl::Hidden};
458 
460  preserveAggregate{
461  "preserve-aggregate",
462  llvm::cl::desc("Specify input file format:"),
463  llvm::cl::values(
464  clEnumValN(circt::firrtl::PreserveAggregate::None, "none",
465  "Preserve no aggregate"),
466  clEnumValN(circt::firrtl::PreserveAggregate::OneDimVec, "1d-vec",
467  "Preserve only 1d vectors of ground type"),
468  clEnumValN(circt::firrtl::PreserveAggregate::Vec, "vec",
469  "Preserve only vectors"),
470  clEnumValN(circt::firrtl::PreserveAggregate::All, "all",
471  "Preserve vectors and bundles")),
473  };
474 
476  "preserve-values",
477  llvm::cl::desc("Specify the values which can be optimized away"),
478  llvm::cl::values(
479  clEnumValN(firrtl::PreserveValues::Strip, "strip",
480  "Strip all names. No name is preserved"),
481  clEnumValN(firrtl::PreserveValues::None, "none",
482  "Names could be preserved by best-effort unlike `strip`"),
483  clEnumValN(firrtl::PreserveValues::Named, "named",
484  "Preserve values with meaningful names"),
485  clEnumValN(firrtl::PreserveValues::All, "all",
486  "Preserve all values")),
487  llvm::cl::init(firrtl::PreserveValues::None)};
488 
489  llvm::cl::opt<bool> enableDebugInfo{
490  "g", llvm::cl::desc("Enable the generation of debug information"),
491  llvm::cl::init(false)};
492 
493  // Build mode options.
495  "O", llvm::cl::desc("Controls how much optimization should be performed"),
496  llvm::cl::values(clEnumValN(firtool::FirtoolOptions::BuildModeDebug,
497  "debug",
498  "Compile with only necessary optimizations"),
499  clEnumValN(firtool::FirtoolOptions::BuildModeRelease,
500  "release", "Compile with optimizations")),
501  llvm::cl::init(firtool::FirtoolOptions::BuildModeDefault)};
502 
503  llvm::cl::opt<bool> disableOptimization{
504  "disable-opt",
505  llvm::cl::desc("Disable optimizations"),
506  };
507 
509  "export-chisel-interface",
510  llvm::cl::desc("Generate a Scala Chisel interface to the top level "
511  "module of the firrtl circuit"),
512  llvm::cl::init(false)};
513 
514  llvm::cl::opt<std::string> chiselInterfaceOutDirectory{
515  "chisel-interface-out-dir",
516  llvm::cl::desc(
517  "The output directory for generated Chisel interface files"),
518  llvm::cl::init("")};
519 
520  llvm::cl::opt<bool> vbToBV{
521  "vb-to-bv",
522  llvm::cl::desc("Transform vectors of bundles to bundles of vectors"),
523  llvm::cl::init(false)};
524 
525  llvm::cl::opt<bool> noDedup{
526  "no-dedup",
527  llvm::cl::desc("Disable deduplication of structurally identical modules"),
528  llvm::cl::init(false)};
529 
531  "grand-central-companion-mode",
532  llvm::cl::desc("Specifies the handling of Grand Central companions"),
533  ::llvm::cl::values(
534  clEnumValN(firrtl::CompanionMode::Bind, "bind",
535  "Lower companion instances to SystemVerilog binds"),
536  clEnumValN(firrtl::CompanionMode::Instantiate, "instantiate",
537  "Instantiate companions in the design"),
538  clEnumValN(firrtl::CompanionMode::Drop, "drop",
539  "Remove companions from the design")),
540  llvm::cl::init(firrtl::CompanionMode::Bind),
541  llvm::cl::Hidden,
542  };
543 
544  llvm::cl::opt<bool> disableAggressiveMergeConnections{
545  "disable-aggressive-merge-connections",
546  llvm::cl::desc(
547  "Disable aggressive merge connections (i.e. merge all field-level "
548  "connections into bulk connections)"),
549  llvm::cl::init(false)};
550 
551  llvm::cl::opt<bool> emitOMIR{
552  "emit-omir", llvm::cl::desc("Emit OMIR annotations to a JSON file"),
553  llvm::cl::init(true)};
554 
555  llvm::cl::opt<std::string> omirOutFile{
556  "output-omir", llvm::cl::desc("File name for the output omir"),
557  llvm::cl::init("")};
558 
559  llvm::cl::opt<bool> lowerMemories{
560  "lower-memories",
561  llvm::cl::desc("Lower memories to have memories with masks as an "
562  "array with one memory per ground type"),
563  llvm::cl::init(false)};
564 
565  llvm::cl::opt<std::string> blackBoxRootPath{
566  "blackbox-path",
567  llvm::cl::desc(
568  "Optional path to use as the root of black box annotations"),
569  llvm::cl::value_desc("path"),
570  llvm::cl::init(""),
571  };
572 
573  llvm::cl::opt<bool> replSeqMem{
574  "repl-seq-mem",
575  llvm::cl::desc("Replace the seq mem for macro replacement and emit "
576  "relevant metadata"),
577  llvm::cl::init(false)};
578 
579  llvm::cl::opt<std::string> replSeqMemFile{
580  "repl-seq-mem-file", llvm::cl::desc("File name for seq mem metadata"),
581  llvm::cl::init("")};
582 
583  llvm::cl::opt<bool> extractTestCode{
584  "extract-test-code", llvm::cl::desc("Run the extract test code pass"),
585  llvm::cl::init(false)};
586 
587  llvm::cl::opt<bool> ignoreReadEnableMem{
588  "ignore-read-enable-mem",
589  llvm::cl::desc("Ignore the read enable signal, instead of "
590  "assigning X on read disable"),
591  llvm::cl::init(false)};
592 
594  llvm::cl::desc(
595  "Disable random initialization code (may break semantics!)"),
596  llvm::cl::values(
597  clEnumValN(firtool::FirtoolOptions::RandomKind::Mem,
598  "disable-mem-randomization",
599  "Disable emission of memory randomization code"),
600  clEnumValN(firtool::FirtoolOptions::RandomKind::Reg,
601  "disable-reg-randomization",
602  "Disable emission of register randomization code"),
604  "disable-all-randomization",
605  "Disable emission of all randomization code")),
606  llvm::cl::init(firtool::FirtoolOptions::RandomKind::None)};
607 
608  llvm::cl::opt<std::string> outputAnnotationFilename{
609  "output-annotation-file",
610  llvm::cl::desc("Optional output annotation file"),
611  llvm::cl::CommaSeparated, llvm::cl::value_desc("filename")};
612 
613  llvm::cl::opt<bool> enableAnnotationWarning{
614  "warn-on-unprocessed-annotations",
615  llvm::cl::desc(
616  "Warn about annotations that were not removed by lower-to-hw"),
617  llvm::cl::init(false)};
618 
619  llvm::cl::opt<bool> addMuxPragmas{
620  "add-mux-pragmas",
621  llvm::cl::desc("Annotate mux pragmas for memory array access"),
622  llvm::cl::init(false)};
623 
625  "verification-flavor",
626  llvm::cl::desc("Specify a verification flavor used in LowerFIRRTLToHW"),
627  llvm::cl::values(
628  clEnumValN(firrtl::VerificationFlavor::None, "none",
629  "Use the flavor specified by the op"),
630  clEnumValN(firrtl::VerificationFlavor::IfElseFatal, "if-else-fatal",
631  "Use Use `if(cond) else $fatal(..)` format"),
632  clEnumValN(firrtl::VerificationFlavor::Immediate, "immediate",
633  "Use immediate verif statements"),
634  clEnumValN(firrtl::VerificationFlavor::SVA, "sva", "Use SVA")),
635  llvm::cl::init(firrtl::VerificationFlavor::None)};
636 
637  llvm::cl::opt<bool> emitSeparateAlwaysBlocks{
638  "emit-separate-always-blocks",
639  llvm::cl::desc(
640  "Prevent always blocks from being merged and emit constructs into "
641  "separate always blocks whenever possible"),
642  llvm::cl::init(false)};
643 
644  llvm::cl::opt<bool> etcDisableInstanceExtraction{
645  "etc-disable-instance-extraction",
646  llvm::cl::desc("Disable extracting instances only that feed test code"),
647  llvm::cl::init(false)};
648 
649  llvm::cl::opt<bool> etcDisableRegisterExtraction{
650  "etc-disable-register-extraction",
651  llvm::cl::desc("Disable extracting registers that only feed test code"),
652  llvm::cl::init(false)};
653 
654  llvm::cl::opt<bool> etcDisableModuleInlining{
655  "etc-disable-module-inlining",
656  llvm::cl::desc("Disable inlining modules that only feed test code"),
657  llvm::cl::init(false)};
658 
659  llvm::cl::opt<bool> addVivadoRAMAddressConflictSynthesisBugWorkaround{
660  "add-vivado-ram-address-conflict-synthesis-bug-workaround",
661  llvm::cl::desc(
662  "Add a vivado specific SV attribute (* ram_style = "
663  "\"distributed\" *) to unpacked array registers as a workaronud "
664  "for a vivado synthesis bug that incorrectly modifies "
665  "address conflict behavivor of combinational memories"),
666  llvm::cl::init(false)};
667 
668  //===----------------------------------------------------------------------===
669  // External Clock Gate Options
670  //===----------------------------------------------------------------------===
671 
672  llvm::cl::opt<std::string> ckgModuleName{
673  "ckg-name", llvm::cl::desc("Clock gate module name"),
674  llvm::cl::init("EICG_wrapper")};
675 
676  llvm::cl::opt<std::string> ckgInputName{
677  "ckg-input", llvm::cl::desc("Clock gate input port name"),
678  llvm::cl::init("in")};
679 
680  llvm::cl::opt<std::string> ckgOutputName{
681  "ckg-output", llvm::cl::desc("Clock gate output port name"),
682  llvm::cl::init("out")};
683 
684  llvm::cl::opt<std::string> ckgEnableName{
685  "ckg-enable", llvm::cl::desc("Clock gate enable port name"),
686  llvm::cl::init("en")};
687 
688  llvm::cl::opt<std::string> ckgTestEnableName{
689  "ckg-test-enable",
690  llvm::cl::desc("Clock gate test enable port name (optional)"),
691  llvm::cl::init("test_en")};
692 
693  llvm::cl::opt<bool> exportModuleHierarchy{
694  "export-module-hierarchy",
695  llvm::cl::desc("Export module and instance hierarchy as JSON"),
696  llvm::cl::init(false)};
697 
698  llvm::cl::opt<bool> stripFirDebugInfo{
699  "strip-fir-debug-info",
700  llvm::cl::desc(
701  "Disable source fir locator information in output Verilog"),
702  llvm::cl::init(true)};
703 
704  llvm::cl::opt<bool> stripDebugInfo{
705  "strip-debug-info",
706  llvm::cl::desc("Disable source locator information in output Verilog"),
707  llvm::cl::init(false)};
708 
709  llvm::cl::opt<bool> fixupEICGWrapper{
710  "fixup-eicg-wrapper",
711  llvm::cl::desc("Lower `EICG_wrapper` modules into clock gate intrinsics"),
712  llvm::cl::init(false)};
713 
714  llvm::cl::opt<bool> addCompanionAssume{
715  "add-companion-assume",
716  llvm::cl::desc("Add companion assumes to assertions"),
717  llvm::cl::init(false)};
718 };
719 } // namespace
720 
721 static llvm::ManagedStatic<FirtoolCmdOptions> clOptions;
722 
723 /// Register a set of useful command-line options that can be used to configure
724 /// various flags within the MLIRContext. These flags are used when constructing
725 /// an MLIR context for initialization.
727  // Make sure that the options struct has been initialized.
728  *clOptions;
729 }
730 
731 // Initialize the firtool options with defaults supplied by the cl::opts above.
733  : outputFilename("-"), disableAnnotationsUnknown(false),
734  disableAnnotationsClassless(false), lowerAnnotationsNoRefTypePorts(false),
735  allowAddingPortsOnPublic(false),
736  preserveAggregate(firrtl::PreserveAggregate::None),
737  preserveMode(firrtl::PreserveValues::None), enableDebugInfo(false),
738  buildMode(BuildModeRelease), disableOptimization(false),
739  exportChiselInterface(false), chiselInterfaceOutDirectory(""),
740  vbToBV(false), noDedup(false), companionMode(firrtl::CompanionMode::Bind),
741  disableAggressiveMergeConnections(false), emitOMIR(true), omirOutFile(""),
742  lowerMemories(false), blackBoxRootPath(""), replSeqMem(false),
743  replSeqMemFile(""), extractTestCode(false), ignoreReadEnableMem(false),
744  disableRandom(RandomKind::None), outputAnnotationFilename(""),
745  enableAnnotationWarning(false), addMuxPragmas(false),
746  verificationFlavor(firrtl::VerificationFlavor::None),
747  emitSeparateAlwaysBlocks(false), etcDisableInstanceExtraction(false),
748  etcDisableRegisterExtraction(false), etcDisableModuleInlining(false),
749  addVivadoRAMAddressConflictSynthesisBugWorkaround(false),
750  ckgModuleName("EICG_wrapper"), ckgInputName("in"), ckgOutputName("out"),
751  ckgEnableName("en"), ckgTestEnableName("test_en"), ckgInstName("ckg"),
752  exportModuleHierarchy(false), stripFirDebugInfo(true),
753  stripDebugInfo(false), fixupEICGWrapper(false),
754  addCompanionAssume(false) {
755  if (!clOptions.isConstructed())
756  return;
757  outputFilename = clOptions->outputFilename;
758  disableAnnotationsUnknown = clOptions->disableAnnotationsUnknown;
759  disableAnnotationsClassless = clOptions->disableAnnotationsClassless;
760  lowerAnnotationsNoRefTypePorts = clOptions->lowerAnnotationsNoRefTypePorts;
761  allowAddingPortsOnPublic = clOptions->allowAddingPortsOnPublic;
762  preserveAggregate = clOptions->preserveAggregate;
763  preserveMode = clOptions->preserveMode;
764  enableDebugInfo = clOptions->enableDebugInfo;
765  buildMode = clOptions->buildMode;
766  disableOptimization = clOptions->disableOptimization;
767  exportChiselInterface = clOptions->exportChiselInterface;
768  chiselInterfaceOutDirectory = clOptions->chiselInterfaceOutDirectory;
769  vbToBV = clOptions->vbToBV;
770  noDedup = clOptions->noDedup;
771  companionMode = clOptions->companionMode;
773  clOptions->disableAggressiveMergeConnections;
774  emitOMIR = clOptions->emitOMIR;
775  omirOutFile = clOptions->omirOutFile;
776  lowerMemories = clOptions->lowerMemories;
777  blackBoxRootPath = clOptions->blackBoxRootPath;
778  replSeqMem = clOptions->replSeqMem;
779  replSeqMemFile = clOptions->replSeqMemFile;
780  extractTestCode = clOptions->extractTestCode;
781  ignoreReadEnableMem = clOptions->ignoreReadEnableMem;
782  disableRandom = clOptions->disableRandom;
783  outputAnnotationFilename = clOptions->outputAnnotationFilename;
784  enableAnnotationWarning = clOptions->enableAnnotationWarning;
785  addMuxPragmas = clOptions->addMuxPragmas;
786  verificationFlavor = clOptions->verificationFlavor;
787  emitSeparateAlwaysBlocks = clOptions->emitSeparateAlwaysBlocks;
788  etcDisableInstanceExtraction = clOptions->etcDisableInstanceExtraction;
789  etcDisableRegisterExtraction = clOptions->etcDisableRegisterExtraction;
790  etcDisableModuleInlining = clOptions->etcDisableModuleInlining;
792  clOptions->addVivadoRAMAddressConflictSynthesisBugWorkaround;
793  ckgModuleName = clOptions->ckgModuleName;
794  ckgInputName = clOptions->ckgInputName;
795  ckgOutputName = clOptions->ckgOutputName;
796  ckgEnableName = clOptions->ckgEnableName;
797  ckgTestEnableName = clOptions->ckgTestEnableName;
798  exportModuleHierarchy = clOptions->exportModuleHierarchy;
799  stripFirDebugInfo = clOptions->stripFirDebugInfo;
800  stripDebugInfo = clOptions->stripDebugInfo;
801  fixupEICGWrapper = clOptions->fixupEICGWrapper;
802  addCompanionAssume = clOptions->addCompanionAssume;
803 }
static LogicalResult exportChiselInterface(CircuitOp circuit, llvm::raw_ostream &os)
Exports a Chisel interface to the output stream.
static llvm::ManagedStatic< FirtoolCmdOptions > clOptions
Definition: Firtool.cpp:721
Set of options used to control the behavior of the firtool pipeline.
Definition: Firtool.h:30
bool shouldStripDebugInfo() const
Definition: Firtool.h:116
firrtl::PreserveAggregate::PreserveMode getPreserveAggregate() const
Definition: Firtool.h:65
bool shouldAddVivadoRAMAddressConflictSynthesisBugWorkaround() const
Definition: Firtool.h:128
firrtl::PreserveValues::PreserveMode preserveMode
Definition: Firtool.h:366
bool shouldAddCompanionAssume() const
Definition: Firtool.h:133
auto getVerificationFlavor() const
Definition: Firtool.h:123
StringRef getOmirOutputFile() const
Definition: Firtool.h:55
bool isDefaultOutputFilename() const
Definition: Firtool.h:85
StringRef getOutputFilename() const
Definition: Firtool.h:54
bool shouldDisableAggressiveMergeConnections() const
Definition: Firtool.h:119
StringRef getReplaceSequentialMemoriesFile() const
Definition: Firtool.h:60
bool addVivadoRAMAddressConflictSynthesisBugWorkaround
Definition: Firtool.h:393
bool shouldExportChiselInterface() const
Definition: Firtool.h:105
bool shouldExtractTestCode() const
Definition: Firtool.h:131
std::string chiselInterfaceOutDirectory
Definition: Firtool.h:371
bool shouldFixupEICGWrapper() const
Definition: Firtool.h:132
firrtl::PreserveValues::PreserveMode getPreserveMode() const
Definition: Firtool.h:42
StringRef getBlackBoxRootPath() const
Definition: Firtool.h:56
bool shouldDisableOptimization() const
Definition: Firtool.h:99
firrtl::CompanionMode getCompanionMode() const
Definition: Firtool.h:68
bool shouldDisableClasslessAnnotations() const
Definition: Firtool.h:89
bool shouldIgnoreReadEnableMemories() const
Definition: Firtool.h:103
bool isRandomEnabled(RandomKind kind) const
Definition: Firtool.h:38
bool shouldDisableUnknownAnnotations() const
Definition: Firtool.h:86
bool shouldAddMuxPragmas() const
Definition: Firtool.h:127
bool shouldEnableAnnotationWarning() const
Definition: Firtool.h:122
bool shouldReplicateSequentialMemories() const
Definition: Firtool.h:98
bool shouldEtcDisableInstanceExtraction() const
Definition: Firtool.h:107
bool shouldConvertVecOfBundle() const
Definition: Firtool.h:106
StringRef getOutputAnnotationFilename() const
Definition: Firtool.h:61
bool shouldStripFirDebugInfo() const
Definition: Firtool.h:117
bool shouldEtcDisableRegisterExtraction() const
Definition: Firtool.h:110
std::string outputAnnotationFilename
Definition: Firtool.h:385
firrtl::VerificationFlavor verificationFlavor
Definition: Firtool.h:388
firrtl::PreserveAggregate::PreserveMode preserveAggregate
Definition: Firtool.h:365
bool shouldLowerMemories() const
Definition: Firtool.h:100
bool shouldEtcDisableModuleInlining() const
Definition: Firtool.h:113
bool shouldAllowAddingPortsOnPublic() const
Definition: Firtool.h:95
bool shouldLowerNoRefTypePortAnnotations() const
Definition: Firtool.h:92
bool shouldExportModuleHierarchy() const
Definition: Firtool.h:118
firrtl::CompanionMode companionMode
Definition: Firtool.h:374
seq::ExternalizeClockGateOptions getClockGateOptions() const
Definition: Firtool.h:70
bool shouldEnableDebugInfo() const
Definition: Firtool.h:102
bool shouldEmitSeparateAlwaysBlocks() const
Definition: Firtool.h:124
StringRef getChiselInterfaceOutputDirectory() const
Definition: Firtool.h:57
std::unique_ptr< mlir::Pass > createDedupPass()
Definition: Dedup.cpp:743
@ All
Preserve all aggregate values.
Definition: Passes.h:42
@ OneDimVec
Preserve only 1d vectors of ground type (e.g. UInt<2>[3]).
Definition: Passes.h:36
@ Vec
Preserve only vectors (e.g. UInt<2>[3][3]).
Definition: Passes.h:39
@ None
Don't preserve aggregate at all.
Definition: Passes.h:33
@ Strip
Strip all names. No name on declaration is preserved.
Definition: Passes.h:50
std::unique_ptr< mlir::Pass > createInferReadWritePass()
std::unique_ptr< mlir::Pass > createCheckCombLoopsPass()
std::unique_ptr< mlir::Pass > createFinalizeIRPass()
Definition: FinalizeIR.cpp:46
std::unique_ptr< mlir::Pass > createLowerFIRRTLTypesPass(PreserveAggregate::PreserveMode mode=PreserveAggregate::None, PreserveAggregate::PreserveMode memoryMode=PreserveAggregate::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createResolveTracesPass(mlir::StringRef outputAnnotationFilename="")
std::unique_ptr< mlir::Pass > createEmitOMIRPass(mlir::StringRef outputFilename="")
std::unique_ptr< mlir::Pass > createResolvePathsPass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLAnnotationsPass(bool ignoreUnhandledAnnotations=false, bool ignoreClasslessAnnotations=false, bool noRefTypePorts=false, bool allowAddingPortsOnPublic=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLowerSignaturesPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createVBToBVPass()
Definition: VBToBV.cpp:995
std::unique_ptr< mlir::Pass > createGrandCentralPass(CompanionMode companionMode=CompanionMode::Bind)
std::unique_ptr< mlir::Pass > createLowerDPIPass()
Definition: LowerDPI.cpp:229
std::unique_ptr< mlir::Pass > createLowerIntmodulesPass(bool fixupEICGWrapper=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createIMConstPropPass()
std::unique_ptr< mlir::Pass > createBlackBoxReaderPass(std::optional< mlir::StringRef > inputPrefix={})
std::unique_ptr< mlir::Pass > createCreateCompanionAssume()
std::unique_ptr< mlir::Pass > createCreateSiFiveMetadataPass(bool replSeqMem=false, mlir::StringRef replSeqMemFile="")
std::unique_ptr< mlir::Pass > createLayerMergePass()
Definition: LayerMerge.cpp:82
std::unique_ptr< mlir::Pass > createInlinerPass()
std::unique_ptr< mlir::Pass > createVectorizationPass()
std::unique_ptr< mlir::Pass > createLowerMemoryPass()
std::unique_ptr< mlir::Pass > createDropNamesPass(PreserveValues::PreserveMode mode=PreserveValues::None)
Definition: DropName.cpp:100
std::unique_ptr< mlir::Pass > createLowerLayersPass()
std::unique_ptr< mlir::Pass > createIMDeadCodeElimPass()
std::unique_ptr< mlir::Pass > createLintingPass()
Definition: Lint.cpp:78
std::unique_ptr< mlir::Pass > createEliminateWiresPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createPassiveWiresPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createExtractInstancesPass()
std::unique_ptr< mlir::Pass > createLayerSinkPass()
Definition: LayerSink.cpp:61
std::unique_ptr< mlir::Pass > createSpecializeLayersPass()
std::unique_ptr< mlir::Pass > createLowerCHIRRTLPass()
std::unique_ptr< mlir::Pass > createInnerSymbolDCEPass()
std::unique_ptr< mlir::Pass > createExpandWhensPass()
std::unique_ptr< mlir::Pass > createLowerXMRPass()
Definition: LowerXMR.cpp:860
std::unique_ptr< mlir::Pass > createLowerIntrinsicsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createInferWidthsPass()
std::unique_ptr< mlir::Pass > createMemToRegOfVecPass(bool replSeqMem=false, bool ignoreReadEnable=false)
std::unique_ptr< mlir::Pass > createLowerOpenAggsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createAssignOutputDirsPass(mlir::StringRef outputDir="")
std::unique_ptr< mlir::Pass > createDropConstPass()
Definition: DropConst.cpp:111
std::unique_ptr< mlir::Pass > createSFCCompatPass()
Definition: SFCCompat.cpp:171
std::unique_ptr< mlir::Pass > createPrefixModulesPass()
std::unique_ptr< mlir::Pass > createInjectDUTHierarchyPass()
std::unique_ptr< mlir::Pass > createRandomizeRegisterInitPass()
std::unique_ptr< mlir::Pass > createLowerClassesPass()
std::unique_ptr< mlir::Pass > createAddSeqMemPortsPass()
std::unique_ptr< mlir::Pass > createRegisterOptimizerPass()
std::unique_ptr< mlir::Pass > createLowerMatchesPass()
std::unique_ptr< mlir::Pass > createMergeConnectionsPass(bool enableAggressiveMerging=false)
std::unique_ptr< mlir::Pass > createInferResetsPass()
std::unique_ptr< mlir::Pass > createFlattenMemoryPass()
std::unique_ptr< mlir::Pass > createMaterializeDebugInfoPass()
LogicalResult populateHWToBTOR2(mlir::PassManager &pm, const FirtoolOptions &opt, llvm::raw_ostream &os)
Definition: Firtool.cpp:411
LogicalResult populateExportSplitVerilog(mlir::PassManager &pm, const FirtoolOptions &opt, llvm::StringRef directory)
Definition: Firtool.cpp:393
LogicalResult populateHWToSV(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:282
LogicalResult populateLowFIRRTLToHW(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:241
LogicalResult populateExportVerilog(mlir::PassManager &pm, const FirtoolOptions &opt, std::unique_ptr< llvm::raw_ostream > os)
Definition: Firtool.cpp:374
LogicalResult populatePreprocessTransforms(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:27
void registerFirtoolCLOptions()
Register a set of useful command-line options that can be used to configure various flags within the ...
Definition: Firtool.cpp:726
LogicalResult populateFinalizeIR(mlir::PassManager &pm, const FirtoolOptions &opt)
Definition: Firtool.cpp:403
LogicalResult populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm, const FirtoolOptions &opt, StringRef inputFilename)
Definition: Firtool.cpp:52
std::unique_ptr< mlir::Pass > createFlattenModulesPass()
std::unique_ptr< mlir::Pass > createVerifyInnerRefNamespacePass()
std::unique_ptr< mlir::Pass > createFreezePathsPass()
std::unique_ptr< mlir::Pass > createVerifyObjectFieldsPass()
std::unique_ptr< mlir::Pass > createHWMemSimImplPass(const HWMemSimImplOptions &options={})
std::unique_ptr< mlir::Pass > createExternalizeClockGatePass(const ExternalizeClockGateOptions &options={})
std::unique_ptr< mlir::Pass > createHWExportModuleHierarchyPass()
std::unique_ptr< mlir::Pass > createSVExtractTestCodePass(bool disableInstanceExtraction=false, bool disableRegisterExtraction=false, bool disableModuleInlining=false)
std::unique_ptr< mlir::Pass > createHWLegalizeModulesPass()
std::unique_ptr< mlir::Pass > createPrettifyVerilogPass()
std::unique_ptr< mlir::Pass > createHWCleanupPass(bool mergeAlwaysBlocks=true)
Definition: HWCleanup.cpp:252
std::unique_ptr< mlir::Pass > createVerifyClockedAssertLikePass()
std::unique_ptr< mlir::Pass > createPrepareForFormalPass()
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
Definition: DebugAnalysis.h:21
std::unique_ptr< mlir::Pass > createExportSplitChiselInterfacePass(mlir::StringRef outputDirectory="./")
std::unique_ptr< mlir::Pass > createExportVerilogPass(std::unique_ptr< llvm::raw_ostream > os)
std::unique_ptr< mlir::Pass > createExportChiselInterfacePass(llvm::raw_ostream &os)
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< mlir::Pass > createConvertHWToBTOR2Pass(llvm::raw_ostream &os)
Definition: HWToBTOR2.cpp:1021
std::unique_ptr< OperationPass< hw::HWModuleOp > > createLowerVerifToSVPass()
Create the Verif to SV conversion pass.
Definition: VerifToSV.cpp:159
std::unique_ptr< mlir::Pass > createLowerSeqToSVPass(const LowerSeqToSVOptions &options={})
Definition: SeqToSV.cpp:645
std::unique_ptr< mlir::Pass > createLowerLTLToCorePass()
Definition: LTLToCore.cpp:163
std::unique_ptr< mlir::Pass > createLowerFIRRTLToHWPass(bool enableAnnotationWarning=false, firrtl::VerificationFlavor assertionFlavor=firrtl::VerificationFlavor::None)
This is the pass constructor.
Definition: LowerToHW.cpp:586
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
Definition: SimToSV.cpp:361
std::unique_ptr< Pass > createSimpleCanonicalizerPass()
Create a simple canonicalizer pass.
Definition: Passes.cpp:15
std::unique_ptr< mlir::Pass > createStripDebugInfoWithPredPass(const std::function< bool(mlir::Location)> &pred)
Creates a pass to strip debug information from a function.
LogicalResult populatePrepareForExportVerilog(mlir::PassManager &pm, const firtool::FirtoolOptions &opt)
Definition: Firtool.cpp:335