20 #include "mlir/Transforms/Passes.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/Path.h"
25 using namespace circt;
41 pm.nest<firrtl::CircuitOp>().addNestedPass<firrtl::FModuleOp>(
44 pm.nest<firrtl::CircuitOp>().addPass(
46 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
54 StringRef inputFilename) {
59 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
62 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
66 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
67 mlir::createCSEPass());
69 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
74 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
80 pm.nest<firrtl::CircuitOp>().addPass(
93 pm.nest<firrtl::CircuitOp>().addPass(
110 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
120 auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
136 auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
150 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
155 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
161 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
170 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
188 pm.addNestedPass<firrtl::CircuitOp>(
193 ? llvm::sys::path::parent_path(inputFilename)
195 pm.nest<firrtl::CircuitOp>().addPass(
200 pm.addNestedPass<firrtl::CircuitOp>(mlir::createSymbolDCEPass());
209 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
211 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
220 pm.nest<firrtl::CircuitOp>().addPass(
224 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
229 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
233 if (outputFilename ==
"-")
236 pm.nest<firrtl::CircuitOp>().addPass(
245 pm.nest<firrtl::CircuitOp>().addPass(
258 pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
266 modulePM.addPass(mlir::createCSEPass());
295 FirtoolOptions::RandomKind::Reg),
303 FirtoolOptions::RandomKind::Mem),
308 ? seq::ReadEnableMode::Ignore
309 : seq::ReadEnableMode::Undefined,
317 modulePM.addPass(mlir::createCSEPass());
319 modulePM.addPass(mlir::createCSEPass());
350 if (
auto fileLoc = dyn_cast<FileLineColLoc>(loc))
351 return fileLoc.getFilename().getValue().ends_with(
".fir");
357 [](mlir::Location loc) {
return true; }));
375 std::unique_ptr<llvm::raw_ostream> os) {
385 llvm::raw_ostream &os) {
395 llvm::StringRef directory) {
413 llvm::raw_ostream &os) {
429 struct FirtoolCmdOptions {
432 llvm::cl::desc(
"Output filename, or directory for split output"),
433 llvm::cl::value_desc(
"filename"),
438 "disable-annotation-unknown",
439 llvm::cl::desc(
"Ignore unknown annotations when parsing"),
440 llvm::cl::init(
false)};
443 "disable-annotation-classless",
444 llvm::cl::desc(
"Ignore annotations without a class when parsing"),
445 llvm::cl::init(
false)};
448 "lower-annotations-no-ref-type-ports",
450 "Create real ports instead of ref type ports when resolving "
451 "wiring problems inside the LowerAnnotations pass"),
452 llvm::cl::init(
false), llvm::cl::Hidden};
455 "allow-adding-ports-on-public-modules",
456 llvm::cl::desc(
"Allow adding ports to public modules"),
457 llvm::cl::init(
false), llvm::cl::Hidden};
461 llvm::cl::desc(
"Convert probes to non-probe signals"),
462 llvm::cl::init(
false), llvm::cl::Hidden};
466 "preserve-aggregate",
467 llvm::cl::desc(
"Specify input file format:"),
470 "Preserve no aggregate"),
472 "Preserve only 1d vectors of ground type"),
474 "Preserve only vectors"),
476 "Preserve vectors and bundles")),
482 llvm::cl::desc(
"Specify the values which can be optimized away"),
485 "Strip all names. No name is preserved"),
486 clEnumValN(firrtl::PreserveValues::None,
"none",
487 "Names could be preserved by best-effort unlike `strip`"),
489 "Preserve values with meaningful names"),
491 "Preserve all values")),
492 llvm::cl::init(firrtl::PreserveValues::None)};
495 "g", llvm::cl::desc(
"Enable the generation of debug information"),
496 llvm::cl::init(
false)};
500 "O", llvm::cl::desc(
"Controls how much optimization should be performed"),
501 llvm::cl::values(clEnumValN(firtool::FirtoolOptions::BuildModeDebug,
503 "Compile with only necessary optimizations"),
504 clEnumValN(firtool::FirtoolOptions::BuildModeRelease,
505 "release",
"Compile with optimizations")),
506 llvm::cl::init(firtool::FirtoolOptions::BuildModeDefault)};
510 llvm::cl::desc(
"Disable optimizations"),
514 "export-chisel-interface",
515 llvm::cl::desc(
"Generate a Scala Chisel interface to the top level "
516 "module of the firrtl circuit"),
517 llvm::cl::init(
false)};
520 "chisel-interface-out-dir",
522 "The output directory for generated Chisel interface files"),
527 llvm::cl::desc(
"Transform vectors of bundles to bundles of vectors"),
528 llvm::cl::init(
false)};
532 llvm::cl::desc(
"Disable deduplication of structurally identical modules"),
533 llvm::cl::init(
false)};
536 "grand-central-companion-mode",
537 llvm::cl::desc(
"Specifies the handling of Grand Central companions"),
539 clEnumValN(firrtl::CompanionMode::Bind,
"bind",
540 "Lower companion instances to SystemVerilog binds"),
541 clEnumValN(firrtl::CompanionMode::Instantiate,
"instantiate",
542 "Instantiate companions in the design"),
543 clEnumValN(firrtl::CompanionMode::Drop,
"drop",
544 "Remove companions from the design")),
545 llvm::cl::init(firrtl::CompanionMode::Bind),
550 "disable-aggressive-merge-connections",
552 "Disable aggressive merge connections (i.e. merge all field-level "
553 "connections into bulk connections)"),
554 llvm::cl::init(
false)};
557 "emit-omir", llvm::cl::desc(
"Emit OMIR annotations to a JSON file"),
558 llvm::cl::init(
true)};
561 "output-omir", llvm::cl::desc(
"File name for the output omir"),
566 llvm::cl::desc(
"Lower memories to have memories with masks as an "
567 "array with one memory per ground type"),
568 llvm::cl::init(
false)};
573 "Optional path to use as the root of black box annotations"),
574 llvm::cl::value_desc(
"path"),
580 llvm::cl::desc(
"Replace the seq mem for macro replacement and emit "
581 "relevant metadata"),
582 llvm::cl::init(
false)};
585 "repl-seq-mem-file", llvm::cl::desc(
"File name for seq mem metadata"),
589 "extract-test-code", llvm::cl::desc(
"Run the extract test code pass"),
590 llvm::cl::init(
false)};
593 "ignore-read-enable-mem",
594 llvm::cl::desc(
"Ignore the read enable signal, instead of "
595 "assigning X on read disable"),
596 llvm::cl::init(
false)};
600 "Disable random initialization code (may break semantics!)"),
602 clEnumValN(firtool::FirtoolOptions::RandomKind::Mem,
603 "disable-mem-randomization",
604 "Disable emission of memory randomization code"),
605 clEnumValN(firtool::FirtoolOptions::RandomKind::Reg,
606 "disable-reg-randomization",
607 "Disable emission of register randomization code"),
609 "disable-all-randomization",
610 "Disable emission of all randomization code")),
611 llvm::cl::init(firtool::FirtoolOptions::RandomKind::None)};
614 "output-annotation-file",
615 llvm::cl::desc(
"Optional output annotation file"),
616 llvm::cl::CommaSeparated, llvm::cl::value_desc(
"filename")};
619 "warn-on-unprocessed-annotations",
621 "Warn about annotations that were not removed by lower-to-hw"),
622 llvm::cl::init(
false)};
626 llvm::cl::desc(
"Annotate mux pragmas for memory array access"),
627 llvm::cl::init(
false)};
630 "verification-flavor",
631 llvm::cl::desc(
"Specify a verification flavor used in LowerFIRRTLToHW"),
633 clEnumValN(firrtl::VerificationFlavor::None,
"none",
634 "Use the flavor specified by the op"),
635 clEnumValN(firrtl::VerificationFlavor::IfElseFatal,
"if-else-fatal",
636 "Use Use `if(cond) else $fatal(..)` format"),
637 clEnumValN(firrtl::VerificationFlavor::Immediate,
"immediate",
638 "Use immediate verif statements"),
639 clEnumValN(firrtl::VerificationFlavor::SVA,
"sva",
"Use SVA")),
640 llvm::cl::init(firrtl::VerificationFlavor::None)};
643 "emit-separate-always-blocks",
645 "Prevent always blocks from being merged and emit constructs into "
646 "separate always blocks whenever possible"),
647 llvm::cl::init(
false)};
650 "etc-disable-instance-extraction",
651 llvm::cl::desc(
"Disable extracting instances only that feed test code"),
652 llvm::cl::init(
false)};
655 "etc-disable-register-extraction",
656 llvm::cl::desc(
"Disable extracting registers that only feed test code"),
657 llvm::cl::init(
false)};
660 "etc-disable-module-inlining",
661 llvm::cl::desc(
"Disable inlining modules that only feed test code"),
662 llvm::cl::init(
false)};
665 "add-vivado-ram-address-conflict-synthesis-bug-workaround",
667 "Add a vivado specific SV attribute (* ram_style = "
668 "\"distributed\" *) to unpacked array registers as a workaronud "
669 "for a vivado synthesis bug that incorrectly modifies "
670 "address conflict behavivor of combinational memories"),
671 llvm::cl::init(
false)};
678 "ckg-name", llvm::cl::desc(
"Clock gate module name"),
679 llvm::cl::init(
"EICG_wrapper")};
682 "ckg-input", llvm::cl::desc(
"Clock gate input port name"),
683 llvm::cl::init(
"in")};
686 "ckg-output", llvm::cl::desc(
"Clock gate output port name"),
687 llvm::cl::init(
"out")};
690 "ckg-enable", llvm::cl::desc(
"Clock gate enable port name"),
691 llvm::cl::init(
"en")};
695 llvm::cl::desc(
"Clock gate test enable port name (optional)"),
696 llvm::cl::init(
"test_en")};
699 "export-module-hierarchy",
700 llvm::cl::desc(
"Export module and instance hierarchy as JSON"),
701 llvm::cl::init(
false)};
704 "strip-fir-debug-info",
706 "Disable source fir locator information in output Verilog"),
707 llvm::cl::init(
true)};
711 llvm::cl::desc(
"Disable source locator information in output Verilog"),
712 llvm::cl::init(
false)};
715 "fixup-eicg-wrapper",
716 llvm::cl::desc(
"Lower `EICG_wrapper` modules into clock gate intrinsics"),
717 llvm::cl::init(
false)};
720 "add-companion-assume",
721 llvm::cl::desc(
"Add companion assumes to assertions"),
722 llvm::cl::init(
false)};
726 static llvm::ManagedStatic<FirtoolCmdOptions>
clOptions;
738 : outputFilename(
"-"), disableAnnotationsUnknown(false),
739 disableAnnotationsClassless(false), lowerAnnotationsNoRefTypePorts(false),
740 allowAddingPortsOnPublic(false), probesToSignals(false),
741 preserveAggregate(firrtl::PreserveAggregate::None),
742 preserveMode(firrtl::PreserveValues::None), enableDebugInfo(false),
743 buildMode(BuildModeRelease), disableOptimization(false),
745 vbToBV(false), noDedup(false), companionMode(firrtl::
CompanionMode::Bind),
746 disableAggressiveMergeConnections(false), emitOMIR(true), omirOutFile(
""),
747 lowerMemories(false), blackBoxRootPath(
""), replSeqMem(false),
748 replSeqMemFile(
""), extractTestCode(false), ignoreReadEnableMem(false),
749 disableRandom(
RandomKind::None), outputAnnotationFilename(
""),
750 enableAnnotationWarning(false), addMuxPragmas(false),
752 emitSeparateAlwaysBlocks(false), etcDisableInstanceExtraction(false),
753 etcDisableRegisterExtraction(false), etcDisableModuleInlining(false),
754 addVivadoRAMAddressConflictSynthesisBugWorkaround(false),
755 ckgModuleName(
"EICG_wrapper"), ckgInputName(
"in"), ckgOutputName(
"out"),
756 ckgEnableName(
"en"), ckgTestEnableName(
"test_en"), ckgInstName(
"ckg"),
757 exportModuleHierarchy(false), stripFirDebugInfo(true),
758 stripDebugInfo(false), fixupEICGWrapper(false),
759 addCompanionAssume(false) {
779 clOptions->disableAggressiveMergeConnections;
798 clOptions->addVivadoRAMAddressConflictSynthesisBugWorkaround;
static LogicalResult exportChiselInterface(CircuitOp circuit, llvm::raw_ostream &os)
Exports a Chisel interface to the output stream.
std::unique_ptr< mlir::Pass > createDedupPass()
@ All
Preserve all aggregate values.
@ OneDimVec
Preserve only 1d vectors of ground type (e.g. UInt<2>[3]).
@ Vec
Preserve only vectors (e.g. UInt<2>[3][3]).
@ None
Don't preserve aggregate at all.
@ Strip
Strip all names. No name on declaration is preserved.
std::unique_ptr< mlir::Pass > createInferReadWritePass()
std::unique_ptr< mlir::Pass > createCheckCombLoopsPass()
std::unique_ptr< mlir::Pass > createFinalizeIRPass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLTypesPass(PreserveAggregate::PreserveMode mode=PreserveAggregate::None, PreserveAggregate::PreserveMode memoryMode=PreserveAggregate::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createResolveTracesPass(mlir::StringRef outputAnnotationFilename="")
std::unique_ptr< mlir::Pass > createEmitOMIRPass(mlir::StringRef outputFilename="")
std::unique_ptr< mlir::Pass > createResolvePathsPass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLAnnotationsPass(bool ignoreUnhandledAnnotations=false, bool ignoreClasslessAnnotations=false, bool noRefTypePorts=false, bool allowAddingPortsOnPublic=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLowerSignaturesPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createVBToBVPass()
std::unique_ptr< mlir::Pass > createGrandCentralPass(CompanionMode companionMode=CompanionMode::Bind)
std::unique_ptr< mlir::Pass > createLowerDPIPass()
std::unique_ptr< mlir::Pass > createLowerIntmodulesPass(bool fixupEICGWrapper=false)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createIMConstPropPass()
std::unique_ptr< mlir::Pass > createBlackBoxReaderPass(std::optional< mlir::StringRef > inputPrefix={})
std::unique_ptr< mlir::Pass > createCreateCompanionAssume()
std::unique_ptr< mlir::Pass > createCreateSiFiveMetadataPass(bool replSeqMem=false, mlir::StringRef replSeqMemFile="")
std::unique_ptr< mlir::Pass > createLayerMergePass()
std::unique_ptr< mlir::Pass > createInlinerPass()
std::unique_ptr< mlir::Pass > createVectorizationPass()
std::unique_ptr< mlir::Pass > createLowerMemoryPass()
std::unique_ptr< mlir::Pass > createDropNamesPass(PreserveValues::PreserveMode mode=PreserveValues::None)
std::unique_ptr< mlir::Pass > createLowerLayersPass()
std::unique_ptr< mlir::Pass > createIMDeadCodeElimPass()
std::unique_ptr< mlir::Pass > createLintingPass()
std::unique_ptr< mlir::Pass > createPassiveWiresPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createExtractInstancesPass()
std::unique_ptr< mlir::Pass > createLayerSinkPass()
std::unique_ptr< mlir::Pass > createSpecializeLayersPass()
std::unique_ptr< mlir::Pass > createLowerCHIRRTLPass()
std::unique_ptr< mlir::Pass > createInnerSymbolDCEPass()
std::unique_ptr< mlir::Pass > createExpandWhensPass()
std::unique_ptr< mlir::Pass > createLowerXMRPass()
std::unique_ptr< mlir::Pass > createLowerIntrinsicsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createInferWidthsPass()
std::unique_ptr< mlir::Pass > createMemToRegOfVecPass(bool replSeqMem=false, bool ignoreReadEnable=false)
std::unique_ptr< mlir::Pass > createLowerOpenAggsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createAssignOutputDirsPass(mlir::StringRef outputDir="")
std::unique_ptr< mlir::Pass > createDropConstPass()
std::unique_ptr< mlir::Pass > createSFCCompatPass()
std::unique_ptr< mlir::Pass > createPrefixModulesPass()
std::unique_ptr< mlir::Pass > createInjectDUTHierarchyPass()
std::unique_ptr< mlir::Pass > createRandomizeRegisterInitPass()
std::unique_ptr< mlir::Pass > createLowerClassesPass()
std::unique_ptr< mlir::Pass > createAddSeqMemPortsPass()
std::unique_ptr< mlir::Pass > createRegisterOptimizerPass()
std::unique_ptr< mlir::Pass > createLowerMatchesPass()
std::unique_ptr< mlir::Pass > createProbesToSignalsPass()
This is the pass constructor.
std::unique_ptr< mlir::Pass > createMergeConnectionsPass(bool enableAggressiveMerging=false)
std::unique_ptr< mlir::Pass > createInferResetsPass()
std::unique_ptr< mlir::Pass > createFlattenMemoryPass()
std::unique_ptr< mlir::Pass > createMaterializeDebugInfoPass()
std::unique_ptr< mlir::Pass > createFlattenModulesPass()
std::unique_ptr< mlir::Pass > createVerifyInnerRefNamespacePass()
std::unique_ptr< mlir::Pass > createFreezePathsPass()
std::unique_ptr< mlir::Pass > createVerifyObjectFieldsPass()
std::unique_ptr< mlir::Pass > createHWMemSimImplPass(const HWMemSimImplOptions &options={})
std::unique_ptr< mlir::Pass > createExternalizeClockGatePass(const ExternalizeClockGateOptions &options={})
std::unique_ptr< mlir::Pass > createHWExportModuleHierarchyPass()
std::unique_ptr< mlir::Pass > createSVExtractTestCodePass(bool disableInstanceExtraction=false, bool disableRegisterExtraction=false, bool disableModuleInlining=false)
std::unique_ptr< mlir::Pass > createHWLegalizeModulesPass()
std::unique_ptr< mlir::Pass > createPrettifyVerilogPass()
std::unique_ptr< mlir::Pass > createHWCleanupPass(bool mergeAlwaysBlocks=true)
std::unique_ptr< mlir::Pass > createVerifyClockedAssertLikePass()
std::unique_ptr< mlir::Pass > createPrepareForFormalPass()
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createExportSplitChiselInterfacePass(mlir::StringRef outputDirectory="./")
std::unique_ptr< mlir::Pass > createExportVerilogPass(std::unique_ptr< llvm::raw_ostream > os)
std::unique_ptr< mlir::Pass > createExportChiselInterfacePass(llvm::raw_ostream &os)
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< mlir::Pass > createConvertHWToBTOR2Pass(llvm::raw_ostream &os)
std::unique_ptr< OperationPass< hw::HWModuleOp > > createLowerVerifToSVPass()
Create the Verif to SV conversion pass.
std::unique_ptr< mlir::Pass > createLowerSeqToSVPass(const LowerSeqToSVOptions &options={})
std::unique_ptr< mlir::Pass > createLowerLTLToCorePass()
std::unique_ptr< mlir::Pass > createLowerFIRRTLToHWPass(bool enableAnnotationWarning=false, firrtl::VerificationFlavor assertionFlavor=firrtl::VerificationFlavor::None)
This is the pass constructor.
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
std::unique_ptr< Pass > createSimpleCanonicalizerPass()
Create a simple canonicalizer pass.
std::unique_ptr< mlir::Pass > createStripDebugInfoWithPredPass(const std::function< bool(mlir::Location)> &pred)
Creates a pass to strip debug information from a function.
LogicalResult populatePrepareForExportVerilog(mlir::PassManager &pm, const firtool::FirtoolOptions &opt)