| C_build | |
| CPython.setup.CustomBuild | |
| Csetup.CustomBuild | |
| Ctest_bsp_common._Bundle | |
| Ctest_bsp_common._Bundles | |
| Cpytest._ChildResult | |
| Cpytest._ClassCompileCache | |
| Ctests.integration.test_hostmem_read._Dut | |
| CAbstractContextManager | |
| CPython.support.BackedgeBuilder | |
| Cesi::AcceleratorConnection | Abstract class representing a connection to an accelerator |
| Cesi::backends::cosim::CosimAccelerator | Connect to an ESI simulation |
| Cesi::backends::trace::TraceAccelerator | Connect to an ESI simulation |
| Cesi::backends::xrt::XrtAccelerator | Connect to an ESI simulation |
| Cesiaccel.accelerator.AcceleratorConnection | |
| Cesi::AcceleratorServiceThread | Background thread which services various requests |
| Ccomb.AddOp | |
| Chwarith.AddOp | |
| CAffineAccessExpr | |
| Ccirct::ImportVerilog::AmbiguousHierCapture | A function whose hierarchical reference resolves to one symbol reachable through more than one instance |
| Ccomb.AndOp | |
| Ccirct::firrtl::AnnoPathValue | |
| Ccirct::firrtl::AnnoRecord | ===-------------------------------------------------------------------—===// LowerAnnotations ===-------------------------------------------------------------------—===// |
| Ccirct::firrtl::AnnoTarget | An annotation target is used to keep track of something that is targeted by an Annotation |
| Ccirct::firrtl::OpAnnoTarget | This represents an annotation targeting a specific operation |
| Ccirct::firrtl::PortAnnoTarget | This represents an annotation targeting a specific port of a module, memory, or instance |
| Ccirct::firrtl::AnnoTargetCache | Cache AnnoTargets for a module's named things |
| Ccirct::firrtl::detail::AnnoTargetImpl | |
| Ccirct::firrtl::Annotation | This class provides a read-only projection of an annotation |
| Ccirct::firrtl::AnnotationSet | This class provides a read-only projection over the MLIR attributes that represent a set of annotations |
| Ccirct::arc::runtime::APICallbacks | |
| CCLI::App | |
| Cesi::CliParser | Common options and code for ESI runtime tools |
| Cesi::AppID | |
| Ccirct::esi::AppIDIndex | An index for resolving AppIDPaths to dynamic instances |
| Ccirct::firrtl::ApplyState | State threaded through functions for resolving and applying annotations |
| Ccirct::arc::ArcCostModel | |
| CArcModelTraceInfo | |
| CArcRuntimeModelInfo | Static information for a compiled hardware model, generated by the MLIR lowering |
| CArcState | Combined runtime and model state for a hardware model instance |
| CArcTraceTap | |
| COpAsmParser::Argument | |
| Ccirct::hw::module_like_impl::PortParse | |
| Chw.ArrayConcatOp | |
| Chw.ArrayCreateOp | |
| Chw.ArrayGetOp | |
| Chw.ArraySliceOp | |
| Csv.AssignOp | |
| Cmlir::AttrTypeSubElementHandler< circt::esi::BundledChannel > | |
| Cmlir::AttrTypeSubElementHandler< circt::FieldInfo > | Expose the names and types of fields to the generic attribute and type walking and replacement infrastructure |
| Cmlir::AttrTypeSubElementHandler< circt::firrtl::BundleType::BundleElement > | Allow walking and replacing the subelements of a BundleElement |
| Cmlir::AttrTypeSubElementHandler< circt::firrtl::ClassElement > | Allow walking and replacing the subelements of a ClassElement |
| Cmlir::AttrTypeSubElementHandler< circt::firrtl::FEnumType::EnumElement > | Allow walking and replacing the subelements of an EnumElement |
| Cmlir::AttrTypeSubElementHandler< circt::firrtl::OpenBundleType::BundleElement > | Allow walking and replacing the subelements of an OpenBundleElement |
| Cmlir::AttrTypeSubElementHandler< circt::hw::detail::OffsetFieldInfo > | Expose the field names and types of union types to the generic attribute and type walking and replacement infrastructure |
| Ccirct::Backedge | Backedge is a wrapper class around a Value |
| Ccirct::BackedgeBuilder | Instantiate one of these and use it to build typed backedges |
| Cesi::registry::internal::BackendRegistry | |
| Ccirct::SparseOpSCC< Direction, NumInlineElts >::BackwardFrame | |
| Cimpl::BalanceMuxBase | |
| CBalanceMuxPass | Pass that performs enhanced mux chain optimizations |
| Cmlir::DialectInterface::Base | |
| Ccirct::ReducePatternDialectInterface | A dialect interface to provide reduction patterns to a reducer tool |
| Ccirct::arc::ArcReducePatternDialectInterface | A dialect interface to provide reduction patterns to a reducer tool |
| Ccirct::firrtl::FIRRTLReducePatternDialectInterface | A dialect interface to provide reduction patterns to a reducer tool |
| Ccirct::hw::HWReducePatternDialectInterface | A dialect interface to provide reduction patterns to a reducer tool |
| Ccirct::om::OMReducePatternDialectInterface | A dialect interface to provide reduction patterns to a reducer tool |
| Ccirct::rtg::RTGReducePatternDialectInterface | A dialect interface to provide reduction patterns to a reducer tool |
| Ccirct::arc::RuntimeCostEstimateDialectInterface | A dialect interface to get runtime cost estimates of MLIR operations |
| Ccirct::firrtl::IntrinsicLoweringDialectInterface | A dialect interface to provide lowering conversions |
| Ccirct::firrtl::FIRRTLIntrinsicLoweringDialectInterface | |
| Ccirct::hw::HWModulePortTypeInterface | |
| Ccirct::hw::ProbeTypeDialectInterface | Interface for dialects to classify their types as valid probe payloads |
| Cmlir::SideEffects::Resource::Base | |
| Ccirct::rtg::MutResource | Abstract memory resource for RTG mutable-cell operations |
| Ccirct::rtg::RNGStateResource | A custom resource representing the RNG state |
| CBaseBasePath | |
| Com.BasePath | |
| CBaseEvaluator | |
| Com.Evaluator | |
| CBaseList | |
| Com.List | |
| CBaseObject | |
| Com.Object | |
| Ccirct::calyx::BasicLoopInterface | |
| Ccirct::calyx::RepeatOpInterface< scf::ForOp > | |
| Ccirct::scftocalyx::ScfForOp | |
| Ccirct::calyx::LoopInterface | |
| Ccirct::calyx::WhileOpInterface< LoopSchedulePipelineOp > | |
| Ccirct::pipelinetocalyx::PipelineWhileOp | |
| Ccirct::calyx::WhileOpInterface< scf::WhileOp > | |
| Ccirct::scftocalyx::ScfWhileOp | |
| Ccirct::calyx::WhileOpInterface< T > | |
| Ccirct::calyx::RepeatOpInterface< T > | |
| Ccirct::BinaryTruthTable | Represents a boolean function as a truth table |
| Cesi::BitVector::bit_iterator | Forward iterator for iterating over bits from LSB (index 0) to MSB |
| Chw.BitcastOp | |
| Cesi::BitVector | A lightweight, non-owning bit vector view backed by a byte array span |
| Cesi::IntView | Non-owning view of a signed bit vector with toI64() and implicit conversions to signed scalar types |
| Cesi::MutableBitVector | A mutable bit vector that owns its underlying storage |
| Cesi::Int | |
| Cesi::UInt | |
| Cesi::UIntView | Non-owning view of an unsigned bit vector with toUI64() and implicit conversions to unsigned scalar types |
| CBlockControlTerm | Holds information about an handshake "basic block terminator" control operation |
| Ccirct::bmc::BMCTrace | |
| Ccirct::pretty::BufferingPP | Buffer tokens for clients that need to adjust things |
| Cbuild_ext | |
| CPython.setup.NoopBuildExtension | |
| Csetup.NoopBuildExtension | |
| Cbuild_py | |
| CPython.setup.CMakeBuild | |
| Csetup.CMakeBuild | |
| Ccirct::esi::BundledChannel | |
| Cesi::BundleEngineMap | Since engines can support multiple channels BUT not necessarily all of the channels in a bundle, a mapping from bundle channels to engines is needed |
| Cesi::BundlePort | Services provide connections to 'bundles' – collections of named, unidirectional communication channels |
| Cesi::services::ServicePort | Add a custom interface to a service client at a particular point in the design hierarchy |
| Cesi::services::CallService::Callback | A function call which gets attached to a service port |
| Cesi::services::ChannelService::FromHost | A port which writes data to the accelerator (from_host) |
| Cesi::services::ChannelService::ToHost | A port which reads data from the accelerator (to_host) |
| Cesi::services::FuncService::Function | A function call which gets attached to a service port |
| Cesi::services::MMIO::MMIORegion | A "slice" of some parent MMIO space |
| Cesi::services::TelemetryService::Metric | A telemetry port which gets attached to a service port |
| Cesiaccel.types.BundlePort | |
| Cesiaccel.types.CallbackPort | |
| Cesiaccel.types.FromHostPort | |
| Cesiaccel.types.FunctionPort | |
| Cesiaccel.types.MMIORegion | |
| Cesiaccel.types.MetricPort | |
| Cesiaccel.types.ToHostPort | |
| Ccirct::SymbolCacheBase::CacheIteratorImpl | |
| Ccirct::SymbolCache::SymbolCacheIteratorImpl | |
| Ccirct::hw::HWSymbolCache::HwSymbolCacheIteratorImpl | |
| Ccirct::CadicalSATSolverOptions | |
| CCallPrepPrecomputed | Build indexes to make lookups faster. Create the new argument types as well |
| Ccirct::scftocalyx::CallScheduleable | |
| Ccirct::calyx::CalyxLoweringState | An interface for conversion passes that lower Calyx programs |
| Ccirct::sv::CaseInfo | |
| Ccirct::sv::CasePattern | |
| Ccirct::sv::CaseBitPattern | |
| Ccirct::sv::CaseDefaultPattern | |
| Ccirct::sv::CaseEnumPattern | |
| Ccirct::sv::CaseExprPattern | |
| Chwarith.CastOp | |
| Cesi::ChannelAssignment | Details about how to connect to a particular channel |
| Cesi::backends::cosim::RpcClient::ChannelDesc | Description of a channel from the server |
| CRpcClient::ChannelDesc | Description of a channel from the server |
| Cesi::cosim::RpcServer::Impl::ChannelInfo | |
| CRpcServer::Impl::ChannelInfo | |
| Cesi::backends::cosim::RpcClient.Impl::ChannelMeta | |
| Cesi::ChannelPort | Unidirectional channels are the basic communication primitive between the host and accelerator |
| Cesi::ReadChannelPort | A ChannelPort which reads data from the accelerator |
| Cesi::UnknownReadChannelPort | Instantiated when a backend does not know how to create a read channel |
| Cesi::WriteChannelPort | A ChannelPort which sends data to the accelerator |
| Cesi::UnknownWriteChannelPort | Instantiated when a backend does not know how to create a write channel |
| Cesi.ChannelSignaling | |
| Ccirct::firrtl::impl::CheckCombLoopsBase | |
| CCheckCombLoopsPass | This pass constructs a local graph for each module to detect combinational cycles |
| Ccirct::firrtl::impl::CheckLayersBase | |
| CCheckLayersPass | |
| Ccirct::chirrtl::CHIRRTLVisitor< ConcreteType, ResultType, ExtraArgs > | CHIRRTLVisitor is a visitor for CHIRRTL operations |
| CCirctESIAppIDIndex | |
| CCirctESIBundleTypeBundleChannel | |
| CCirctMSFTPlacementDB | |
| CCirctMSFTPrimitiveDB | |
| CCirctMSFTWalkOrder | |
| Ccirct::firrtl::InstanceInfo::CircuitAttributes | Information about a circuit |
| Ccirct::firrtl::CircuitTargetCache | Cache AnnoTargets for a circuit's modules, walked as needed |
| Ccirct::firrtl::ClassElement | |
| Ccirct::firrtl::Annotation::ClassIsa | Helper struct to perform variadic class equality check |
| Ccirct::ImportVerilog::ClassLowering | |
| Cesi::cosim::RpcServer::Impl::ClientSession | |
| CRpcServer::Impl::ClientSession | |
| Ccirct::firrtl::ClockEdge | |
| Ccirct::llhd::deseq::ClockInfo | A single clock extracted from a process during trigger analysis |
| Ccirct::firrtl::GatedClockConversion::ClockPairPlan | (baseClk, enable) pair planned for a clock value |
| Ccirct::comb::CombinationalVisitor< ConcreteType, ResultType, ExtraArgs > | This helps visit Combinational nodes |
| Ccomb::CombinationalVisitor | |
| CEmittedExpressionStateManager | This class handles information about AST structures of each expressions |
| CCompileControlVisitor | |
| Ccirct::calyx::ComponentLoweringStateInterface | |
| Ccirct::pipelinetocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Ccirct::scftocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Cseq.CompRegClockEnabledOp | |
| Cseq.CompRegLike | |
| Cseq.CompRegOp | |
| Ccirct::datapath::CompressorBit | |
| Ccirct::datapath::CompressorTree | |
| Ccomb.ConcatOp | |
| Cesi::ChannelPort::ConnectOptions | |
| Cesi::Constant | |
| Chw.ConstantOp | |
| Chwarith.ConstantOp | |
| Ccirct::llhd::ConstProjectionRange | Portion of a signal selected by a projection, with a statically known offset and width in bits |
| Ccirct::firrtl::ContainAliasableTypes< head, tail > | A struct to check if there is a type derived from FIRRTLBaseType |
| Ccirct::firrtl::ContainAliasableTypes< BaseTy > | |
| Ccirct::ImportVerilog::Context | A helper class to facilitate the conversion from a Slang AST to MLIR operations |
| CContext | This class provides a thread-safe interface to access the analysis results |
| Cesi::Context | AcceleratorConnections, Accelerators, and Manifests must all share a context |
| Cesiaccel.accelerator.Context | |
| CConversionPattern | |
| CPartialLowerRegion | Allows to partially lower a region by matching on the parent operation to then call the provided partial lowering function with the region and the rewriter |
| Cmlir::ConversionPattern | |
| Ccirct::TypeConversionPattern | Generic pattern which replaces an operation by one of the same operation name, but with converted attributes, operands, and result types to eliminate illegal types |
| CConversionTarget | |
| CLowerRegionTarget | |
| CConvertToLLVMBase | |
| Ccirct::impl::ConvertToLLVMPass | |
| CCoord | Test the CoordTranslator module using message translation |
| CCoordTranslateArg | Translated argument struct for CoordTranslator |
| CCoordTranslateResult | Translated result struct for CoordTranslator |
| Cesi::ChannelPort::TranslationInfo::CopyOp | A copy operation for translating between frame data and the translation |
| Cpytest.CosimPytestConfig | |
| Cesiaccel.codegen.ports.CppPortGroup | |
| Cesiaccel.codegen.ports.CppPortKind | |
| Cesiaccel.codegen.generator.CppTypeEmitter | |
| Cesiaccel.codegen.generator.CppTypePlanner | |
| Ccirct::Cube | Represents a product term (cube) in a sum-of-products expression |
| Ccirct::synth::Cut | Represents a cut in the combinational logic network |
| Ccirct::synth::CutEnumerator | Cut enumeration engine for combinational logic networks |
| Ccirct::synth::CutEnumeratorStats | |
| Ccirct::synth::CutRewritePattern | Base class for cut rewriting patterns used in combinational logic optimization |
| CGenericLUT | A generic K-input LUT pattern that can implement any boolean function with up to K inputs using a lookup table |
| CTechLibraryPattern | Simple technology library encoded as a HWModuleOp |
| Ccirct::synth::CutRewritePatternSet | Manages a collection of rewriting patterns for combinational logic optimization |
| Ccirct::synth::CutRewriter | Main cut-based rewriting algorithm for combinational logic optimization |
| Ccirct::synth::CutRewriterOptions | Configuration options for the cut-based rewriting algorithm |
| Ccirct::synth::CutSet | Manages a collection of cuts for a single logic node using priority cuts algorithm |
| Ccirct::CyclicOpSCC | A cyclic SCC: a pointer-sized, directly-iterable reference to a group of mutually-reachable operations (or a single op with a self-loop) |
| Ccirct::analysis::CyclicSchedulingAnalysis | CyclicSchedulingAnalysis constructs a CyclicProblem for each AffineForOp by performing a memory dependence analysis and inserting dependences into the problem |
| Ccirct::synth::DataflowPath | |
| Csynth.DataflowPath | |
| Ccirct::lsp::DebounceOptions | Debounce tuning for document-change bursts |
| Ccirct::DebugAnalysis | Identify operations and values that are only used for debug info |
| Ccirct::DebugInfo | Debug information attached to an operation and the operations nested within |
| Ccirct::detail::DebugInfoBuilder | Helper to populate a DebugInfo with nodes |
| Ccirct::om::Evaluator::DebugNesting | RAII helper to increment/decrement debugNesting |
| Ccirct::synth::DebugPoint | |
| Csynth.DebugPoint | |
| Cmsft.DeclPhysicalRegionOp | |
| Ccirct::firrtl::DeclVisitor< ConcreteType, ResultType, ExtraArgs > | ExprVisitor is a visitor for FIRRTL declaration nodes |
| Ccirct::firrtl::DeclVisitor< ConcreteType, void, ExtraArgs... > | |
| Ccirct::firrtl::FIRRTLVisitor< ConcreteType, ResultType, ExtraArgs > | FIRRTLVisitor allows you to visit all of the expr/stmt/decls with one class declaration |
| CDeduper | |
| Ccirct::ssp::Default< ProblemT > | Dummy struct to query a problem's default properties (i.e |
| Ccirct::ssp::Default< scheduling::ChainingCyclicProblem > | |
| Ccirct::ssp::Default< scheduling::ChainingProblem > | |
| Ccirct::ssp::Default< scheduling::CyclicProblem > | |
| Ccirct::ssp::Default< scheduling::ModuloProblem > | |
| Ccirct::ssp::Default< scheduling::Problem > | |
| Ccirct::ssp::Default< scheduling::SharedOperatorsProblem > | |
| CDefaultDoCastIfPossible | |
| Cllvm::CastInfo< To, From, std::enable_if_t< std::is_base_of_v<::circt::firrtl::AnnoTarget, From > > > | Add support for llvm style casts to AnnoTarget |
| Cllvm::DefaultDOTGraphTraits | |
| Cllvm::DOTGraphTraits< circt::fsm::FSMGraph * > | |
| Cllvm::DOTGraphTraits< circt::hw::HWModuleOp > | |
| Cllvm::DOTGraphTraits< circt::igraph::InstanceGraph * > | |
| Cllvm::DOTGraphTraits< circt::firrtl::InstanceGraph * > | |
| Cllvm::DOTGraphTraits< circt::hw::InstanceGraph * > | |
| Cesi::AcceleratorServiceThread::DeferStart | Tag type used to construct the base class without starting the service thread |
| Cllvm::DenseMapInfo< T, Enable > | |
| Cllvm::DenseMapInfo< AffineAccessExpr > | |
| Cllvm::DenseMapInfo< bool > | |
| Cllvm::DenseMapInfo< circt::FieldRef > | Allow using FieldRef with DenseMaps |
| Cllvm::DenseMapInfo< circt::FirMemConfig > | |
| Cllvm::DenseMapInfo< circt::firrtl::AnnoTarget > | Make AnnoTarget hash |
| Cllvm::DenseMapInfo< circt::firrtl::Annotation > | Make Annotation hash just like Attribute |
| Cllvm::DenseMapInfo< circt::firrtl::FIRRTLType > | |
| Cllvm::DenseMapInfo< circt::firrtl::FModuleOp > | |
| Cllvm::DenseMapInfo< circt::FVInt, void > | Provide DenseMapInfo for FVInt |
| Cllvm::DenseMapInfo< circt::igraph::InstancePath > | DenseMap traits for InstancePath |
| Cllvm::DenseMapInfo< circt::llhd::deseq::FixedValue > | |
| Cllvm::DenseMapInfo< circt::llhd::deseq::FixedValues > | |
| Cllvm::DenseMapInfo< circt::llhd::deseq::ValueField > | |
| Cllvm::DenseMapInfo< circt::scheduling::Problem::OperatorType > | |
| Cllvm::DenseMapInfo< circt::scheduling::Problem::ResourceType > | |
| Cllvm::DenseMapInfo< circt::synth::Object > | |
| Cllvm::DenseMapInfo< Dependence > | |
| Cllvm::DenseMapInfo< DriveCondition > | |
| Cllvm::DenseMapInfo< JValue > | |
| Cllvm::DenseMapInfo< ModuleInfoRef > | Allow ModuleInfoRef to be used as dense map keys |
| Cllvm::DenseMapInfo< ModuleSummaryPass::KeyTy > | |
| Cllvm::DenseMapInfo< OperandKey > | |
| Cllvm::DenseMapInfo< ResetSignal > | |
| Cllvm::DenseMapInfo< slang::BufferID > | |
| Cllvm::DenseMapInfo< StructuralHashKey > | |
| Cllvm::DenseMapInfo< TrimmedPathRef > | DenseMapInfo specialization for TrimmedPathRef to enable deduplication |
| Ccirct::scheduling::detail::Dependence | A wrapper class to uniformly handle def-use and auxiliary dependence edges |
| Cllvm::Dependence | A wrapper class to uniformly handle def-use and auxiliary dependence edges |
| Cesi::detail::DeserializerSelector< T, typename > | |
| Cesi::detail::DeserializerSelector< T, std::void_t< typename T::TypeDeserializer > > | |
| Cslang::DiagnosticClient | |
| Ccirct::lsp::LSPDiagnosticClient | |
| Cmlir::DialectInterfaceCollection | |
| Ccirct::ReducePatternInterfaceCollection | |
| Ccirct::firrtl::IntrinsicLoweringInterfaceCollection | |
| Ccirct::rtg::DictEntry | Defines an entry in an !rtg.dict |
| Ccirct::DIInstance | |
| Ccirct::DIModule | |
| CDiscoverLoops | |
| Ccirct::DIVariable | |
| Chwarith.DivOp | |
| Ccomb.DivSOp | |
| Ccomb.DivUOp | |
| Ccirct::llhd::deseq::DNF | A boolean function expressed in canonical disjunctive normal form |
| Ccirct::llhd::deseq::DNFTerm | A single AND operation within a DNF |
| Ccirct::moore::DPIArgInfo | Information about one DPI-imported function argument |
| Ccirct::sim::DPIArgument | A single argument in a DPI function type |
| CDPICallLowering | |
| Ccirct::llhd::deseq::DriveInfo | A drive op and the clock and reset that resulted from trigger analysis |
| Cmsft.DynamicInstanceOp | |
| Ccirct::llhd::DynProjectionRange | Portion of a signal selected by a projection with a dynamic index |
| CPython.support.BackedgeBuilder.Edge | |
| Ccirct::ExportSystemC::EmissionPatternSet< PatternTy > | This class collects a set of emission patterns with base type 'PatternTy' |
| Ccirct::ExportSystemC::EmissionPrinter | This is intended to be the driving class for all pattern-based IR emission |
| Ccirct::debug::EmitHGLDDOptions | Options for HGLDD emission |
| CEmittedExpressionState | |
| Cstd::enable_shared_from_this | |
| Ccirct::om::evaluator::EvaluatorValue | Base class for evaluator runtime values |
| Ccirct::om::evaluator::AttributeValue | Values which can be directly representable by MLIR attributes |
| Ccirct::om::evaluator::BasePathValue | A Basepath value |
| Ccirct::om::evaluator::ListValue | A List which contains variadic length of elements with the same type |
| Ccirct::om::evaluator::ObjectValue | A composite Object, which has a type and fields |
| Ccirct::om::evaluator::PathValue | A Path value |
| Ccirct::firrtl::GatedClockConversion::EnableNode | Enable accumulation DAG node: value(id) = parent == kNoEnable ? |
| Cesi::Engine | Engines implement the actual channel communication between the host and the accelerator |
| Cesi::backends::cosim::CosimEngine | Implement the magic cosim channel communication |
| Ccirct::NPNTable::Entry4 | |
| CEquivalence | This class is for reporting differences between two modules which should have been deduplicated |
| Cesi.ESIPureModuleOp | |
| Cesiaccel.types.ESIType | |
| Cesiaccel.types.AnyType | |
| Cesiaccel.types.ArrayType | |
| Cesiaccel.types.BitsType | |
| Cesiaccel.types.BundleType | |
| Cesiaccel.types.ChannelType | |
| Cesiaccel.types.IntType | |
| Cesiaccel.types.SIntType | |
| Cesiaccel.types.UIntType | |
| Cesiaccel.types.ListType | |
| Cesiaccel.types.StructType | |
| Cesiaccel.types.TypeAlias | |
| Cesiaccel.types.UnionType | |
| Cesiaccel.types.VoidType | |
| Cesiaccel.types.WindowType | |
| Ccirct::om::Evaluator | An Evaluator, which is constructed with an IR module and can instantiate Objects |
| Ccirct::aiger::ExportAIGERHandler | Handler for AIGER export |
| Ccirct::aiger::ExportAIGEROptions | Options for AIGER export |
| Ccirct::firrtl::ExprVisitor< ConcreteType, ResultType, ExtraArgs > | ExprVisitor is a visitor for FIRRTL expression nodes |
| Ccirct::firrtl::ExprVisitor< ConcreteType, void, ExtraArgs... > | |
| Ccirct::firrtl::FIRRTLVisitor< ConcreteType, ResultType, ExtraArgs > | FIRRTLVisitor allows you to visit all of the expr/stmt/decls with one class declaration |
| CExtension | |
| CPython.setup.CMakeExtension | |
| Csetup.CMakeExtension | |
| Ccomb.ExtractOp | |
| Cstd::false_type | |
| CHasParameters< Properties, std::void_t< decltype(std::declval< Properties >().parameters)> > | |
| Ccirct::calyx::ComponentLoweringStateInterface::IsFloatingPoint< T, std::void_t< decltype(std::declval< T >().getFloatingPointStandard())> > | |
| Cesi::detail::has_type_deserializer< T, std::void_t< typename T::TypeDeserializer > > | |
| Cesi::has_esi_id< T, std::void_t< decltype(T::_ESI_ID)> > | |
| Cesi::has_esi_window_id< T, std::void_t< decltype(T::_ESI_WINDOW_ID)> > | |
| Cesi::is_std_array< std::array< T, N > > | |
| CHasParameters< Properties, typename > | |
| Ccirct::calyx::ComponentLoweringStateInterface::IsFloatingPoint< T, typename > | |
| Cesi::detail::has_type_deserializer< T, typename > | |
| Cesi::has_esi_id< T, typename > | |
| Cesi::has_esi_window_id< T, typename > | |
| Cesi::is_std_array< T > | |
| Cesi::cosim::FaultStash | Cross-thread error channel for the IXWebSocket network thread |
| Cesi::WindowType::Field | Field information describing a field within a frame |
| Cllvm::yaml::MappingContextTraits< DescribedSignal, Context >::Field | A one-to-one representation with a YAML representation of a signal/field |
| Ccirct::FieldInfo | A named and typed field of an aggregate type |
| Ccirct::ExportVerilog::FieldNameResolver | |
| Cmlir::FieldParser<::BundledChannel, ::BundledChannel > | |
| Ccirct::FieldRef | This class represents a reference to a specific field or element of an aggregate value |
| Ccirct::firrtl::FieldRefCache | Caching version of getFieldRefFromValue |
| Ccirct::firrtl::FieldSource | To use this class, retrieve a cached copy from the analysis manager: auto &fieldsource = getAnalysis<FieldSource>(getOperation()); |
| CFileEmitter | |
| Ccirct::ExportVerilog::FileInfo | Information to control the emission of a list of operations into a file |
| Ccirct::firrtl::FIRLexer | This implements a lexer for .fir files |
| Ccirct::firrtl::FIRLexerCursor | This is the state captured for a lexer cursor |
| Ccirct::FirMemConfig | The configuration of a FIR memory |
| Ccirct::FirMemLowering | FIR memory lowering helper |
| Ccirct::firrtl::FirMemory | |
| Ccirct::seq::FirMemory | Helper structure carrying information about FIR memory generated ops |
| Ccirct::firrtl::FIRParserOptions | |
| Ccirct::FirRegLowering | Lower FirRegOp to sv.reg and sv.always |
| CFIRRTLBundleField | Describes a field in a bundle type |
| CFIRRTLClassElement | Describes an element in a class type |
| Ccirct::firrtl::FIRToken | This represents a specific token for .fir files |
| Ccirct::firtool::FirtoolOptions | Set of options used to control the behavior of the firtool pipeline |
| Ccirct::firrtl::FIRVersion | The FIRRTL specification version |
| Ccirct::llhd::deseq::FixedValue | A single i1 value that is fixed to a given value in the past and the present |
| Ccirct::ImportVerilog::FlattenedIfacePort | Lowering information for a single signal flattened from an interface port |
| CFlattenMemRefsState | |
| Ccirct::arc::runtime::FmtDescriptor | A format descriptor, to be given to arcRuntimeFormat |
| Ccirct::pretty::PrettyPrinter::FormattedToken | Format token with tracked size |
| Ccirct::scftocalyx::ForScheduleable | |
| Ccirct::SparseOpSCC< Direction, NumInlineElts >::ForwardFrame | |
| Cesi::WindowType::Frame | Frame information describing which fields are included in a particular frame |
| Cesi::ChannelPort::TranslationInfo::FrameInfo | Information about each frame in the windowed type |
| Ccirct::ExportSystemC::FrozenEmissionPatternSet< PatternTy, KeyTy > | This class intends to collect a set of emission patterns in a way to provide fast lookups, but does not allow to add more patterns after construction |
| Ccirct::fsm::FSMGraph | Graph representing FSM machines, their states and transitions between these |
| Ccirct::arc::runtime::impl::FSTSignalTableEntry | A traced signal in the FST file |
| CFunc | |
| Cesi_test.JoinAddFunc | |
| Chandshake.FuncOp | |
| Ccirct::ImportVerilog::FunctionLowering | Function lowering information |
| CFunctionRewrite | A struct for maintaining function declarations which needs to be rewritten, if they contain memref arguments that was flattened |
| CFuture | |
| Cesiaccel.types.MessageFuture | |
| Ccirct::FVInt | Four-valued arbitrary precision integers |
| Ccirct::firrtl::GatedClockConversion | Sink gated-clock enables into ops across module boundaries |
| Cesiaccel.codegen.generator.Generator | |
| Cesiaccel.codegen.generator.CppGenerator | |
| Ccirct::firrtl::GenericIntrinsic | Helper class for checking and extracting information from the generic instrinsic op |
| Cimpl::GenericLutMapperBase | |
| CGenericLUTMapperPass | |
| Ccirct::ExportVerilog::GlobalNameResolver | This class keeps track of modules and interfaces that need to be renamed, as well as module ports, parameters, declarations and verif labels that need to be renamed |
| Ccirct::ExportVerilog::GlobalNameTable | This class keeps track of global names at the module/interface level |
| Cllvm::GraphTraits< circt::fsm::FSMStateNode * > | |
| Cllvm::GraphTraits< circt::fsm::FSMGraph * > | |
| Cllvm::GraphTraits< circt::hw::detail::HWOperation * > | |
| Cllvm::GraphTraits< circt::hw::HWModuleOp > | |
| Cllvm::GraphTraits< circt::igraph::InstanceGraphNode * > | Graph traits for modules |
| Cllvm::GraphTraits< circt::igraph::InstanceGraph * > | Graph traits for the instance graph |
| Cllvm::GraphTraits< circt::firrtl::InstanceGraph * > | |
| Cllvm::GraphTraits< circt::hw::InstanceGraph * > | |
| Cllvm::GraphTraits< llvm::Inverse< circt::igraph::InstanceGraphNode * > > | Graph traits for iterating modules in inverse order |
| Ccirct::handshake::HandshakeLowering | |
| Ccirct::handshake::HandshakeVisitor< ConcreteType, ResultType, ExtraArgs > | HandshakeVisitor is a visitor for handshake nodes |
| CHashTableStack< KeyT, ValueT > | This is a stack of hashtables, if lookup fails in the top-most hashtable, it will attempt to lookup in lower hashtables |
| Cmlir::OpTrait::HasParentInterface< InterfaceType > | |
| Ccirct::firrtl::HierPathCache | A cache of existing HierPathOps, mostly used to facilitate HierPathOp reuse |
| Ccirct::hw::HierPathCache | |
| Ccirct::ImportVerilog::HierPathInfo | Hierarchical path information |
| Cloopback.HostComms | |
| Ctest_codegen.HostComms | |
| Cesi::services::HostMemAllocator | Interface for anything which can allocate HostMemRegions |
| Cesi::services::HostMem | |
| CTraceHostMem | |
| Cesi::services::HostMemRegion | RAII memory region for host memory in accelerator-accessible address space |
| CTraceHostMem::TraceHostMemRegion | |
| Cesi::HWClientDetail | A description of a hardware client |
| Ccirct::sv::impl::HWExportModuleHierarchyBase | |
| CHWExportModuleHierarchyPass | |
| Cesi::HWModule | Represents either the top level or an instance of a hardware module |
| Cesi::Accelerator | Top level accelerator class |
| Cesi::Instance | Subclass of HWModule which represents a submodule instance |
| Cesiaccel.accelerator.HWModule | |
| Cesiaccel.accelerator.Accelerator | |
| Cesiaccel.accelerator.Instance | |
| Chw.HWModuleExternOp | |
| Chw.HWModuleOp | |
| CHWModuleOp | |
| CHWModulePort | |
| Ccirct::hw::HWModulePortAccessor | |
| CHWStructFieldInfo | |
| Ccirct::HWToLLVMArraySpillCache | Helper class mapping array values (HW or LLVM Dialect) to pointers to buffers containing the array value |
| Ccirct::HWToLLVMEndianessConverter | |
| CHWUnionFieldInfo | |
| Chwarith.ICmpOp | |
| Csv.IfDefOp | |
| Ccirct::scftocalyx::IfLoweringStateInterface | |
| Ccirct::scftocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Ccirct::scftocalyx::IfScheduleable | |
| CIgraphInstancePath | |
| Cllvm::ilist_node | |
| Ccirct::fsm::FSMStateNode | This is a Node in the FSMGraph. Each node represents a state in the FSM |
| Ccirct::igraph::InstanceGraphNode | This is a Node in the InstanceGraph |
| Cllvm::ilist_node_with_parent | |
| Ccirct::fsm::FSMTransitionEdge | This is an edge in the FSMGraph |
| Ccirct::igraph::InstanceRecord | This is an edge in the InstanceGraph |
| Ccirct::ExportSystemC::FrozenEmissionPatternSet< PatternTy, KeyTy >::Impl | The internal implementation of the frozen pattern set |
| Ccirct::lsp::VerilogServer::Impl | |
| Cesi::backends::trace::TraceAccelerator::Impl | |
| Cesi::backends::xrt::XrtAccelerator::Impl | |
| Cesi::cosim::RpcServer::Impl | |
| CLocationEmitter::Impl | |
| Csynth.LongestPathAnalysis::Impl | Internal implementation for LongestPathAnalysis |
| CManifest::Impl | |
| Cesi::backends::cosim::RpcClient::Impl | |
| CRpcServer::Impl | |
| Ccirct::ImplicitLocOpBuilder | |
| Ccirct::esi::detail::ESIHWBuilder | Assist the lowering steps for conversions which need to create auxiliary IR |
| Ccirct::aiger::ImportAIGEROptions | Options for AIGER import |
| Ccirct::ImportVerilogOptions | Options that control how Verilog input files are parsed and processed |
| Ccirct::IncrementalSATSolver | Abstract interface for incremental SAT solvers with an IPASIR-style API |
| Cesiaccel.codegen.indented_writer.IndentedWriter | |
| Cllvm::indexed_accessor_iterator | |
| Ccirct::firrtl::AnnotationSetIterator | |
| Cesi::IndexedPorts< T > | |
| Ccirct::ExportSystemC::InlineEmitter | This class is returned to a pattern that requested inlined emission of a value |
| Ccirct::hw::InnerRefNamespace | This class represents the namespace in which InnerRef's can be resolved |
| Ccirct::hw::InnerRefNamespaceLike | Classify operations that are InnerRefNamespace-like, until structure is in place to do this via Traits |
| Ccirct::firrtl::impl::InnerSymbolDCEBase | |
| CInnerSymbolDCEPass | |
| Ccirct::hw::InnerSymbolNamespaceCollection | |
| Ccirct::hw::InnerSymbolTable | A table of inner symbols and their resolutions |
| Ccirct::hw::InnerSymbolTableCollection | This class represents a collection of InnerSymbolTable's |
| Ccirct::reduce::InnerSymbolUses | A helper struct that scans a root operation and all its nested operations for InnerRefAttrs |
| Ccirct::hw::InnerSymTarget | The target of an inner symbol, the entity the symbol is a handle for |
| Ccirct::calyx::PredicateInfo::InputPorts | |
| Cllvm::yaml::MappingContextTraits< DescribedInstance, Context >::Instance | A YAML-serializable representation of an interface instantiation |
| Csynth.Instance | |
| Ccirct::firrtl::InstanceChoiceMacroTable | |
| Ccirct::firrtl::GatedClockConversion::InstanceDrive | Caller-side connects driving a planned input port pair |
| Ccirct::igraph::InstanceGraph | This graph tracks modules and where they are instantiated |
| Ccirct::firrtl::InstanceGraph | This graph tracks modules and where they are instantiated |
| Ccirct::hw::InstanceGraph | HW-specific instance graph with a virtual entry node linking to all publicly visible modules |
| Cmsft.InstanceHierarchyOp | |
| Ccirct::firrtl::InstanceInfo | |
| Ccirct::igraph::InstancePath | An instance path composed of a series of instances |
| CInstancePath | An instance path composed of a series of instances |
| Ccirct::igraph::InstancePathCache | A data structure that caches and provides paths to module instances in the IR |
| CInstancePathCache | A data structure that caches and provides paths to module instances in the IR |
| Ccirct::synth::ResourceUsageAnalysis::ModuleResourceUsage::InstanceResource | Information about a child module instance |
| Cllvm::yaml::MappingContextTraits< sv::InterfaceOp, Context >::Interface | A YAML-serializable representation of an interface |
| Ccirct::ImportVerilog::InterfaceLowering | Lowering information for an expanded interface instance |
| Ccirct::arc::runtime::FmtDescriptor::IntFmt | Integer formatting options |
| Ccirct::firrtl::IntrinsicConverter | Base class for Intrinsic Converters |
| Ccirct::firrtl::IntrinsicOpConverter< OpTy > | |
| Ccirct::firrtl::IntrinsicLowerings | Lowering helper which collects all intrinsic converters |
| Cstd::is_convertible | |
| Cesi::has_esi_id< T, std::void_t< decltype(T::_ESI_ID)> > | |
| Cesi::has_esi_window_id< T, std::void_t< decltype(T::_ESI_WINDOW_ID)> > | |
| Cstd::is_same | |
| Ccirct::calyx::ComponentLoweringStateInterface::IsFloatingPoint< T, std::void_t< decltype(std::declval< T >().getFloatingPointStandard())> > | |
| Ccirct::hw::HWSymbolCache::Item | |
| CHashTableStack< KeyT, ValueT >::Iterator | |
| Cllvm::iterator_facade_base | |
| Ccirct::SymbolCacheBase::Iterator | |
| Ccirct::fsm::FSMStateNode::UseIterator | Iterator for state uses |
| Ccirct::igraph::InstanceGraphNode::UseIterator | Iterator for module uses |
| Ccirct::scheduling::detail::DependenceIterator | An iterator to transparently surface an operation's def-use dependences from the SSA subgraph (induced by the registered operations), as well as auxiliary, operation-to-operation dependences explicitly provided by the client |
| Ccirct::firrtl::InstanceInfo::LatticeValue | A lattice value to record the value of a property |
| Ccirct::firrtl::LayerSetCompare | Compares two SymbolRefAttr lexicographically, returning true if LHS should be ordered before RHS |
| Ccirct::firrtl::LegacyWiringProblem | A representation of a legacy Wiring problem consisting of a signal source that should be connected to one or many sinks |
| Ccirct::ExportVerilog::OpLocMap::LineColPair | |
| Ccirct::pretty::PrettyPrinter::Listener | Listener to Token storage events |
| Ccirct::pretty::TokenStringSaver | PrettyPrinter::Listener that saves strings while live |
| Ccirct::pretty::PrintEventAndStorageListener< CallableType, DataType > | |
| Ccirct::pretty::PrintEventAndStorageListener< CallableTy, DataTy > | Note: Callable class must implement a callable with signature: void (Data) |
| Cmlir::PatternRewriter::Listener | |
| Ccirct::synth::IncrementalLongestPathAnalysis | |
| Cesi::ChannelPort::TranslationInfo::ListFieldInfo | Information about a list field within a frame (for parallel encoding) |
| Ccirct::arc::runtime::FmtDescriptor::LiteralFmt | Literal string formatting options |
| CLocalVisitor | |
| CLocationEmitter | |
| Ccirct::ImportVerilog::LocationKey | ImportVerilog Elaboration Phases for Hierarchical Names |
| Ccirct::ExportVerilog::OpLocMap::LocationRange | |
| CFIRParser::LocWithInfo | This helper class is used to handle Info records, which specify higher level symbolic source location, that may be missing from the file |
| Cesi::Logger | |
| Cesi::NullLogger | A logger that does nothing |
| Cesi::TSLogger | A thread-safe logger which calls functions implemented by subclasses |
| Cesi::ConsoleLogger | A logger that writes to the console. Includes color support |
| Cesi::StreamLogger | A logger that writes to a C++ std::ostream |
| Ccirct::synth::LogicNetwork | Flat logic network representation for efficient cut enumeration |
| Ccirct::synth::LogicNetworkGate | Represents a single gate/node in the flat logic network |
| Ccirct::synth::LongestPathAnalysis | |
| Ccirct::synth::IncrementalLongestPathAnalysis | |
| Csynth.LongestPathAnalysis | |
| Ccirct::synth::LongestPathAnalysisOptions | Configuration options for the longest path analysis |
| CLongestPathAnalysisWrapper | |
| Ccirct::synth::LongestPathCollection | |
| Csynth.LongestPathCollection | |
| Csynth.LongestPathHistory | |
| Ccirct::ImportVerilog::LoopFrame | Information about a loops continuation and exit blocks relevant while lowering the loop's body statements |
| Ccirct::calyx::LoopLoweringStateInterface< Loop > | |
| Ccirct::calyx::LoopLoweringStateInterface< PipelineWhileOp > | |
| Ccirct::pipelinetocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Ccirct::calyx::LoopLoweringStateInterface< ScfForOp > | |
| Ccirct::scftocalyx::ForLoopLoweringStateInterface | |
| Ccirct::scftocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Ccirct::calyx::LoopLoweringStateInterface< ScfWhileOp > | |
| Ccirct::scftocalyx::WhileLoopLoweringStateInterface | |
| Ccirct::scftocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Ccirct::impl::LoopScheduleToCalyxBase | |
| Ccirct::pipelinetocalyx::LoopScheduleToCalyxPass | |
| Cimpl::LowerDomainsBase | |
| CLowerDomainsPass | |
| CLowerDPIFunc | |
| Ccirct::LoweringOptions | Options which control the emission from CIRCT to Verilog |
| Ccirct::pipelinetocalyx::LoopScheduleToCalyxPass::LoweringPattern | |
| Ccirct::firrtl::impl::LowerLayersBase | |
| CLowerLayersPass | |
| Cimpl::LowerSeqToSVBase | |
| Ccirct::SeqToSVPass | |
| Ccirct::firrtl::impl::LowerXMRBase | |
| CLowerXMRPass | |
| Ccirct::lsp::LSPServerOptions | |
| Cfsm.MachineOp | |
| Cesi::Manifest | Class to parse a manifest |
| Cllvm::mapped_iterator | |
| Ccirct::fsm::detail::AddressIterator< FSMTransitionList::iterator > | |
| Ccirct::fsm::detail::AddressIterator< NodeList::iterator > | |
| Ccirct::igraph::detail::AddressIterator< InstanceList::iterator > | |
| Ccirct::igraph::detail::AddressIterator< NodeList::iterator > | |
| Ccirct::fsm::detail::AddressIterator< It > | This just maps a iterator of references to an iterator of addresses |
| Ccirct::igraph::detail::AddressIterator< It > | This just maps a iterator of references to an iterator of addresses |
| Cllvm::mapped_iterator_base | |
| Ccirct::detail::OpSCCIterator< BaseIteratorT > | |
| Cllvm::yaml::MappingContextTraits< DescribedInstance, Context > | Conversion from a DescribedInstance to YAML |
| Cllvm::yaml::MappingContextTraits< DescribedSignal, Context > | Conversion from a DescribedSignal to YAML |
| Cllvm::yaml::MappingContextTraits< sv::InterfaceOp, Context > | Conversion from an sv::InterfaceOp to YAML |
| Ccirct::MapVector< KeyT, ValueT, MapType, VectorType, N > | |
| Cllvm::MapVector< KeyT, ValueT, MapType, VectorType, N > | |
| Ccirct::synth::MatchedPattern | Represents a cut that has been successfully matched to a rewriting pattern |
| Ccirct::ExportSystemC::MatchResult | This class allows a pattern's match function for inlining to pass its result's precedence to the pattern that requested the expression |
| Ccirct::synth::MatchResult | Result of matching a cut against a pattern |
| Ccirct::firrtl::GatedClockConversion::MatRef | A reference to a clock/enable value that can also name values which do not exist yet (a planned port, a planned wire) |
| Cesi_ram.MemComms | |
| Ccirct::handshake::MemLoadInterface | |
| Ccirct::analysis::MemoryDependence | MemoryDependence captures a dependence from one memory operation to another |
| Ccirct::analysis::MemoryDependenceAnalysis | MemoryDependenceAnalysis traverses any AffineForOps in the FuncOp body and checks for affine memory access dependences |
| Ccirct::calyx::MemoryInterface | |
| Ccirct::calyx::MemoryPortsImpl | |
| Ccirct::handshake::MemStoreInterface | |
| Ccirct::handshake::HandshakeLowering::MergeOpInfo | |
| Ccirct::reduce::MetasyntacticNameGenerator | A utility class that generates metasyntactic variable names for use in reductions |
| Ccirct::arc::ModelInfo | Gathers information about a given Arc model |
| Ccirct::arc::ModelInfoAnalysis | |
| Ccirct::arc::runtime::impl::ModelInstance | |
| Ccomb.ModSOp | |
| CModule | |
| Cbackpressure.GatedLoopback | |
| Cbackpressure.Producer | |
| Cbackpressure.Top | |
| Cchannel_arbiter.ChannelArbiterTokenTest | |
| Cchannel_arbiter.ListChecker | |
| Cchannel_arbiter.ThroughputProbe | |
| Cchannel_arbiter.TokenChecker | |
| Cchannel_arbiter.Top | |
| Ccustom_channel_service.Loopbacks | |
| Cesi_advanced.Fork | |
| Cesi_advanced.Join | |
| Cesi_advanced.Merge | |
| Cesi_advanced.Top | |
| Cesi_ram.Dummy | |
| Cesi_ram.MemWriter | |
| Cesi_test.CallbackTest | |
| Cesi_test.ConstProducer | |
| Cesi_test.Join | |
| Cesi_test.LoopbackInOutAdd | |
| Cesi_test.MMIOReadWriteClient | |
| Cesi_test.StructToWindowFunc | |
| Cesi_test.Top | |
| Cesi_test.WindowToStructFunc | |
| Cesiaccel.bsp.common.ESI_Manifest_ROM | |
| Cesiaccel.bsp.common.ESI_Manifest_ROM_Wrapper | |
| Cesiaccel.bsp.common.MMIOIndirection | |
| Cesiaccel.bsp.xrt.MMIOAxiReadWriteDemux | |
| Cesiaccel.bsp.xrt.MMIOAxiReadWriteMux | |
| Cesiaccel.bsp.xrt.MMIOAxiWriteCombine | |
| Cesiaccel.esitester.AutoSerialCoordTranslator | |
| Cesiaccel.esitester.CallbackTest | |
| Cesiaccel.esitester.ChannelTest | |
| Cesiaccel.esitester.CoordTranslator | |
| Cesiaccel.esitester.EsiTester | |
| Cesiaccel.esitester.LoopbackInOutAdd | |
| Cesiaccel.esitester.SerialCoordTranslator | |
| Cloopback.CallableFunc1 | |
| Cloopback.Loopback | |
| Cloopback.LoopbackArray | |
| Cloopback.LoopbackOddStruct | |
| Cloopback.LoopbackSInt4 | |
| Cloopback.LoopbackStruct | |
| Cloopback.MemoryAccess1 | |
| Cloopback.Top | |
| Cserialization_probes.ArrayProbe | |
| Cserialization_probes.BitPackProbe | |
| Cserialization_probes.BytePatternConst | |
| Cserialization_probes.BytePatternEchoEq | |
| Cserialization_probes.ByteRotate1 | |
| Cserialization_probes.PackProbe | |
| Cserialization_probes.SignProbe | |
| Cserialization_probes.SignProbe13 | |
| Cserialization_probes.Top | |
| Ctest_codegen.CallServiceCallback | |
| Ctest_codegen.CallbackWindowedList | |
| Ctest_codegen.ChannelMultiBurstListRead | |
| Ctest_codegen.ChannelMultiBurstListWrite | |
| Ctest_codegen.ChannelNarrowCountListWrite | |
| Ctest_codegen.ChannelWindowedListRead | |
| Ctest_codegen.ChannelWindowedListWrite | |
| Ctest_codegen.CustomServiceDeclChannel | |
| Ctest_codegen.IndexedFuncGroup | |
| Ctest_codegen.MmioReadWrite | |
| Ctest_codegen.TelemetryMetric | |
| Ctest_codegen.Top | |
| Ctest_codegen.TypedFuncArrayResult | |
| Ctest_codegen.TypedFuncMultiArg | |
| Ctest_codegen.TypedFuncNestedStruct | |
| Ctest_codegen.TypedFuncStruct | |
| Ctest_codegen.TypedFuncSubByteSigned | |
| Ctest_codegen.TypedFuncVoidArg | |
| Ctest_codegen.TypedFuncVoidResult | |
| Ctest_codegen.TypedFuncWindowedList | |
| Ctest_codegen.TypedReadChannelStruct | |
| Ctest_codegen.TypedWriteChannelByte | |
| CAppIDIndex::ModuleAppIDs | Helper class constructed on a per-HWModuleLike basis |
| Ccirct::firrtl::InstanceInfo::ModuleAttributes | Information about a module |
| CEquivalence::ModuleData | |
| Cesi::ModuleInfo | |
| CModuleInfo | |
| CModuleInfoRef | A reference to a ModuleInfo that compares and hashes like it |
| Chw.ModuleLike | |
| Ccirct::ImportVerilog::ModuleLowering | Module lowering information |
| Ccirct::firrtl::ModuleModifications | A store of pending modifications to a FIRRTL module associated with solving one or more WiringProblems |
| Ccirct::hw::ModulePort | |
| Ccirct::hw::PortInfo | This holds the name, type, direction of a module's ports |
| Ccirct::hw::ModulePortInfo | This holds a decoded list of input/inout and output ports for a module or instance |
| Ccirct::hw::ModulePortLookupInfo | |
| Ccirct::synth::ResourceUsageAnalysis::ModuleResourceUsage | Resource usage for a single module, including local and total counts |
| CModuleSizeCache | Utility to track the transitive size of modules |
| Ccomb.ModUOp | |
| Ccomb.MulOp | |
| Chwarith.MulOp | |
| Ccomb.MuxOp | |
| Cloopback.MyService | |
| Ccirct::ExportVerilog::NameCollisionResolver | |
| CNamedTuple | |
| Cesiaccel.types.BundleType.Channel | |
| Cesiaccel.types.WindowType.Field | |
| Cesiaccel.types.WindowType.Frame | |
| CNamedValueOpView | |
| Ccomb.BinaryOpBuilder | |
| Ccomb.ICmpOpBuilder | |
| Ccomb.UnaryOpBuilder | |
| Ccomb.ExtractOpBuilder | |
| Chwarith.BinaryOpBuilder | |
| Cseq.CompRegLikeBuilder | |
| Cseq.CompRegBuilder | |
| Cseq.CompRegClockEnabledBuilder | |
| CPython.support.NamedValueOpView | |
| Csupport.NamedValueOpView | |
| Chw.InstanceBuilder | |
| Ccirct::Namespace | A namespace that is used to store existing names and generate new names in some scope within the IR |
| Ccirct::firrtl::CircuitNamespace | The namespace of a CircuitOp, generally inhabited by modules |
| Ccirct::hw::InnerSymbolNamespace | |
| CNLARemover | A tracker for track NLAs affected by a reduction |
| Ccirct::firrtl::NLATable | This table tracks nlas and what modules participate in them |
| Ccirct::NPNClass | Represents the canonical form of a boolean function under NPN equivalence |
| Ccirct::NPNTable | Precomputed NPN canonicalization table for 4-input single-output functions |
| CNullableValueCastFailed | |
| Cllvm::CastInfo< To, From, std::enable_if_t< std::is_base_of_v<::circt::firrtl::AnnoTarget, From > > > | Add support for llvm style casts to AnnoTarget |
| Ccirct::synth::Object | |
| Csynth.Object | |
| Ccirct::hw::detail::OffsetFieldInfo | Struct defining a field with an offset. Used in unions |
| COMEvaluator | A value type for use in C APIs that just wraps a pointer to an Evaluator |
| COMEvaluatorValue | A value type for use in C APIs that just wraps a pointer to an Object |
| Ccirct::OpConversionPattern< SourceOp > | |
| CStreamLowering< StdoutStreamOp, 0x80000001 > | |
| CStreamLowering< StderrStreamOp, 0x80000002 > | |
| Ccirct::esi::detail::RemoveOpLowering< OpTy > | Generic pattern for removing an op during pattern conversion |
| Ccirct::msft::RemoveOpLowering< OpTy > | Generic pattern for removing an op during pattern conversion |
| Cmlir::OpConversionPattern< SourceOp > | |
| CStreamLowering< StdoutStreamOp, 0x80000001 > | |
| CStreamLowering< StderrStreamOp, 0x80000002 > | |
| Ccirct::esi::detail::RemoveOpLowering< OpTy > | Generic pattern for removing an op during pattern conversion |
| Ccirct::msft::RemoveOpLowering< OpTy > | Generic pattern for removing an op during pattern conversion |
| Cmlir::OpConversionPattern< affine::AffineParallelOp > | |
| CAffineParallelOpLowering | |
| CAffinePloopUnparallelize | |
| Cmlir::OpConversionPattern< AffineLoadOp > | |
| CAffineLoadLowering | Apply the affine map from an 'affine.load' operation to its operands, and feed the results to a newly created 'memref.load' operation (which replaces the original 'affine.load') |
| Cmlir::OpConversionPattern< AffineStoreOp > | |
| CAffineStoreLowering | Apply the affine map from an 'affine.store' operation to its operands, and feed the results to a newly created 'memref.store' operation (which replaces the original 'affine.store') |
| Cmlir::OpConversionPattern< arc::RuntimeModelOp > | |
| CRuntimeModelOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefAllocOp > | |
| CArrayRefAllocOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefCopyOp > | |
| CArrayRefCopyOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefCreateOp > | |
| CArrayRefCreateOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefFromArrayOp > | |
| CArrayRefFromArrayOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefGetOp > | |
| CArrayRefGetOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefInjectOp > | |
| CArrayRefInjectOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefSliceOp > | |
| CArrayRefSliceOpLowering | |
| Cmlir::OpConversionPattern< ArrayRefToArrayOp > | |
| CArrayRefToArrayOpLowering | |
| Cmlir::OpConversionPattern< calyx::AssignOp > | |
| CConvertAssignOp | |
| Cmlir::OpConversionPattern< ComponentOp > | |
| CConvertComponentOp | ConversionPatterns |
| Cmlir::OpConversionPattern< ControlOp > | |
| CConvertControlOp | |
| Cmlir::OpConversionPattern< FlushOp > | |
| CFlushLowering | |
| Cmlir::OpConversionPattern< IfOp > | |
| CIfOpHoisting | Helper to hoist computation out of scf::IfOp branches, turning it into a mux-like operation, and exposing potentially concurrent execution of its branches |
| Cmlir::OpConversionPattern< mlir::UnrealizedConversionCastOp > | |
| CUnrealizedConversionCastLowering | |
| Cmlir::OpConversionPattern< OpTy > | |
| CStreamLowering< OpTy, StreamValue > | |
| Ccirct::TypeOpConversionPattern< OpTy > | |
| Cmlir::OpConversionPattern< scf::IndexSwitchOp > | |
| CSwitchToIfConversion | |
| Cmlir::OpConversionPattern< StringConcatOp > | |
| CStringConcatLowering | |
| Cmlir::OpConversionPattern< StringConstantOp > | |
| CStringConstantLowering | |
| Cmlir::OpConversionPattern< UnrealizedConversionCastOp > | |
| CArrayRefToLLVMArrayOpLowering | |
| Cmlir::OpConversionPattern< WiresOp > | |
| CConvertWiresOp | |
| Ccirct::analysis::OpCountAnalysis | |
| Ccirct::synth::OpenPath | |
| COperandPairLess | |
| COperationAnalyzer | |
| Ccirct::arc::OperationCosts | |
| Ccirct::OperationPass< T > | |
| Cmlir::OperationPass< T > | |
| Ccirct::scheduling::Problem::OperatorType | Operator types are distinguished by name (chosen by the client) |
| Ccirct::ExportVerilog::OpFileInfo | Information to control the emission of a single operation into a file |
| COpInterfaceConversionPattern | |
| CConvertCellOp | |
| Cmlir::OpInterfaceRewritePattern | |
| Ccirct::calyx::PartialLoweringPattern< calyx::GroupInterface, mlir::OpInterfaceRewritePattern > | |
| Ccirct::calyx::InlineCombGroups | This pass recursively inlines use-def chains of combinational logic (from non-stateful groups) into groups referenced in the control schedule |
| Ccirct::ExportVerilog::OpLocMap | Track the output verilog line,column number information for every op |
| CPython.support.OpOperand | |
| Ccirct::OpRewritePattern< SourceOp > | |
| Ccirct::calyx::PartialLoweringPattern< mlir::func::FuncOp > | |
| Ccirct::calyx::FuncOpPartialLoweringPattern | FuncOpPartialLoweringPatterns are patterns which intend to match on FuncOps and then perform their own walking of the IR |
| Ccirct::calyx::BuildBasicBlockRegs | Builds registers for each block argument in the program |
| Ccirct::calyx::BuildCallInstance | Builds instance for the calyx.invoke and calyx.group in order to initialize the instance |
| Ccirct::calyx::BuildReturnRegs | Builds registers for the return statement of the program and constant assignments to the component return value |
| Ccirct::calyx::ConvertIndexTypes | Converts all index-typed operations and values to i32 values |
| Ccirct::pipelinetocalyx::BuildControl | Builds a control schedule by traversing the CFG of the function and associating this with the previously created groups |
| Ccirct::pipelinetocalyx::BuildOpGroups | Iterate through the operations of a source function and instantiate components or primitives based on the type of the operations |
| Ccirct::pipelinetocalyx::BuildPipelineGroups | Builds groups for assigning registers for pipeline stages |
| Ccirct::pipelinetocalyx::BuildPipelineRegs | Builds registers for each pipeline stage in the program |
| Ccirct::pipelinetocalyx::BuildWhileGroups | In BuildWhileGroups, a register is created for each iteration argumenet of the while op |
| Ccirct::pipelinetocalyx::CleanupFuncOps | Erases FuncOp operations |
| Ccirct::pipelinetocalyx::FuncOpConversion | Creates a new Calyx component for each FuncOp in the program |
| Ccirct::pipelinetocalyx::LateSSAReplacement | LateSSAReplacement contains various functions for replacing SSA values that were not replaced during op construction |
| Ccirct::scftocalyx::BuildControl | Builds a control schedule by traversing the CFG of the function and associating this with the previously created groups |
| Ccirct::scftocalyx::BuildForGroups | In BuildForGroups, a register is created for the iteration argument of the for op |
| Ccirct::scftocalyx::BuildIfGroups | |
| Ccirct::scftocalyx::BuildOpGroups | Iterate through the operations of a source function and instantiate components or primitives based on the type of the operations |
| Ccirct::scftocalyx::BuildWhileGroups | In BuildWhileGroups, a register is created for each iteration argumenet of the while op |
| Ccirct::scftocalyx::CleanupFuncOps | Erases FuncOp operations |
| Ccirct::scftocalyx::FuncOpConversion | Creates a new Calyx component for each FuncOp in the program |
| Ccirct::scftocalyx::LateSSAReplacement | LateSSAReplacement contains various functions for replacing SSA values that were not replaced during op construction |
| Ccirct::calyx::PartialLoweringPattern< calyx::AssignOp > | |
| Ccirct::calyx::RewriteMemoryAccesses | This pass rewrites memory accesses that have a width mismatch |
| Ccirct::calyx::PartialLoweringPattern< OpType, RewritePatternType > | Base class for partial lowering passes |
| Ccirct::dc::EliminateBranchToSelectPattern | |
| Ccirct::dc::EliminateForkOfSourcePattern | |
| Ccirct::dc::EliminateForkToForkPattern | |
| Ccirct::dc::EliminatePackOfUnpackPattern | |
| Ccirct::dc::EliminateRedundantUnpackPattern | |
| Ccirct::dc::JoinOnBranchPattern | |
| Ccirct::dc::RemoveDuplicateJoinOperandsPattern | |
| Ccirct::dc::RemoveJoinOnSourcePattern | |
| Ccirct::dc::StaggeredJoinCanonicalization | |
| Ccirct::scftocalyx::InlineExecuteRegionOpPattern | Inlines Calyx ExecuteRegionOp operations within their parent blocks |
| Cmlir::OpRewritePattern< SourceOp > | |
| Ccirct::calyx::PartialLoweringPattern< mlir::func::FuncOp > | |
| Ccirct::calyx::PartialLoweringPattern< calyx::AssignOp > | |
| Ccirct::calyx::PartialLoweringPattern< OpType, RewritePatternType > | Base class for partial lowering passes |
| Ccirct::dc::EliminateBranchToSelectPattern | |
| Ccirct::dc::EliminateForkOfSourcePattern | |
| Ccirct::dc::EliminateForkToForkPattern | |
| Ccirct::dc::EliminatePackOfUnpackPattern | |
| Ccirct::dc::EliminateRedundantUnpackPattern | |
| Ccirct::dc::JoinOnBranchPattern | |
| Ccirct::dc::RemoveDuplicateJoinOperandsPattern | |
| Ccirct::dc::RemoveJoinOnSourcePattern | |
| Ccirct::dc::StaggeredJoinCanonicalization | |
| Ccirct::scftocalyx::InlineExecuteRegionOpPattern | Inlines Calyx ExecuteRegionOp operations within their parent blocks |
| COpRewritePattern | |
| COrOfMuxToMuxChain | |
| Cmlir::OpRewritePattern< BitsPrimOp > | |
| CBitsOfCat | |
| Cmlir::OpRewritePattern< calyx::CombGroupOp > | |
| Ccirct::calyx::EliminateUnusedCombGroups | Removes calyx::CombGroupOps which are unused |
| Cmlir::OpRewritePattern< calyx::GroupDoneOp > | |
| Ccirct::calyx::NonTerminatingGroupDonePattern | GroupDoneOp's are terminator operations and should therefore be the last operator in a group |
| Cmlir::OpRewritePattern< calyx::GroupOp > | |
| Ccirct::calyx::MultipleGroupDonePattern | When building groups which contain accesses to multiple sequential components, a group_done op is created for each of these |
| Cmlir::OpRewritePattern< calyx::ParOp > | |
| Ccirct::calyx::DeduplicateParallelOp | Removes duplicate EnableOps in parallel operations |
| Cmlir::OpRewritePattern< calyx::StaticParOp > | |
| Ccirct::calyx::DeduplicateStaticParallelOp | Removes duplicate EnableOps in static parallel operations |
| Cmlir::OpRewritePattern< comb::AddOp > | |
| CFoldAddIntoCompress | |
| Cmlir::OpRewritePattern< CompressOp > | |
| CConstantFoldCompress | |
| CSextCompress | |
| Cmlir::OpRewritePattern< CtrlOp > | |
| CCollapseUnaryControl< CtrlOp > | This pattern collapses a calyx.seq or calyx.par operation when it contains exactly one calyx.enable operation |
| Cmlir::OpRewritePattern< datapath::CompressOp > | |
| CFoldCompressIntoCompress | |
| Cmlir::OpRewritePattern< ForkOp > | |
| Ccirct::dc::EliminateUnusedForkResultsPattern | |
| Cmlir::OpRewritePattern< func::ReturnOp > | |
| CBankReturnPattern | |
| Cmlir::OpRewritePattern< IfOp > | |
| CEmptyIfBody | This pattern checks for one of two cases that will lead to IfOp deletion: (1) Then and Else bodies are both empty |
| Cmlir::OpRewritePattern< mlir::affine::AffineLoadOp > | |
| CBankAffineLoadPattern | |
| Cmlir::OpRewritePattern< mlir::affine::AffineStoreOp > | |
| CBankAffineStorePattern | |
| Cmlir::OpRewritePattern< PartialProductOp > | |
| CPosPartialProducts | |
| CReduceNumPartialProducts | |
| CSignedPartialProducts | |
| Cmlir::OpRewritePattern< PosPartialProductOp > | |
| CReduceNumPosPartialProducts | |
| CSignedPosPartialProducts | |
| Cmlir::OpRewritePattern< StaticIfOp > | |
| CEmptyStaticIfBody | This pattern checks for one of two cases that will lead to StaticIfOp deletion: (1) Then and Else bodies are both empty |
| Cllvm::cl::opt | |
| Ccirct::LoweringOptionsOption | |
| Cesi::services::HostMemAllocator::Options | Options for allocating host memory |
| Ccirct::OpUserInfo | |
| COpView | |
| Ccomb.EqOp | |
| Ccomb.GeSOp | |
| Ccomb.GeUOp | |
| Ccomb.GtSOp | |
| Ccomb.GtUOp | |
| Ccomb.LeSOp | |
| Ccomb.LeUOp | |
| Ccomb.LtSOp | |
| Ccomb.LtUOp | |
| Ccomb.NeOp | |
| Ccomb.OrOp | |
| Cfsm.OutputOp | |
| Ccirct::firrtl::OwningModuleCache | This implements an analysis to determine which module owns a given path operation |
| Ccirct::OwningOpRef< OpTy > | |
| Cmlir::OwningOpRef< OpTy > | |
| Ccomb.ParityOp | |
| Ccirct::scftocalyx::ParScheduleable | |
| Cllvm::cl::parser | |
| Ccirct::LoweringOptionsParser | Commandline parser for LoweringOptions |
| Cmlir::PassInstrumentation | |
| Ccirct::VerbosePassInstrumentation< LoggedOpTypes > | |
| Cmlir::PassPipelineOptions | |
| Ccirct::ArcConversionOptions | |
| Ccirct::ArcOptimizationOptions | |
| Ccirct::ArcPreprocessingOptions | |
| Ccirct::ArcStateAllocationOptions | |
| Ccirct::ArcStateLoweringOptions | |
| Ccirct::ArcToLLVMOptions | |
| Ccirct::LlhdToCorePipelineOptions | Convert LLHD dialect IR into core dialect IR |
| Ccirct::rtg::EmissionPipelineOptions | Options for the RTG emission pipeline |
| Ccirct::rtg::RandomizationPipelineOptions | Options for the RTG randomization pipeline |
| Ccirct::synth::CombLoweringPipelineOptions | Options for the aig lowering pipeline |
| Ccirct::synth::SynthOptimizationPipelineOptions | Options for the synth optimization pipeline |
| Ccirct::om::PathElement | A module name, and the name of an instance inside that module |
| Ccirct::firrtl::FieldSource::PathNode | |
| Ccirct::ExportSystemC::PatternBase | This is indented to be the base class for all emission patterns |
| Ccirct::ExportSystemC::AttrEmissionPatternBase | This is intended to be the base class for all emission patterns matching on attributes |
| Ccirct::ExportSystemC::AttrEmissionPattern< A > | This is a convenience class providing default implementations for attribute emission patterns |
| Ccirct::ExportSystemC::OpEmissionPatternBase | This is intended to be the base class for all emission patterns matching on operations |
| Ccirct::ExportSystemC::OpEmissionPattern< VariableOp > | |
| CVariableEmitter | Emit a systemc.cpp.variable operation |
| CVariableEmitter | Emit a systemc.cpp.variable operation |
| Ccirct::ExportSystemC::OpEmissionPattern< AssignOp > | |
| CAssignEmitter | Emit a systemc.cpp.assign operation |
| Ccirct::ExportSystemC::OpEmissionPattern< BindPortOp > | |
| CBindPortEmitter | Emit a systemc.instance.bind_port operation using the operator() rather than .bind() variant |
| Ccirct::ExportSystemC::OpEmissionPattern< CallOp > | |
| CCallEmitter | Emit a systemc.cpp.call operation |
| Ccirct::ExportSystemC::OpEmissionPattern< CallIndirectOp > | |
| CCallIndirectEmitter | Emit a systemc.cpp.call_indirect operation |
| Ccirct::ExportSystemC::OpEmissionPattern< FuncOp > | |
| CFuncEmitter | Emit a systemc.cpp.func function |
| Ccirct::ExportSystemC::OpEmissionPattern< MemberAccessOp > | |
| CMemberAccessEmitter | Emit a systemc.cpp.member_access operation |
| Ccirct::ExportSystemC::OpEmissionPattern< ReturnOp > | |
| CReturnEmitter | Emit a systemc.cpp.return operation |
| Ccirct::ExportSystemC::OpEmissionPattern< Op > | This is a convenience class providing default implementations for operation emission patterns |
| Ccirct::ExportSystemC::TypeEmissionPatternBase | This is intended to be the base class for all emission patterns matching on types |
| Ccirct::ExportSystemC::TypeEmissionPattern< Ty > | This is a convenience class providing default implementations for type emission patterns |
| Cmsft.PDPhysLocationOp | |
| Ccirct::lsp::PendingChanges | Accumulated edits + timing for a single document key |
| Ccirct::lsp::PendingChangesMap | Thread-safe accumulator + debouncer for text document changes |
| Ccirct::ImportVerilog::Context::PendingMonitor | Information about a pending $monitor call that needs to be converted after the current module's body has been processed |
| Ccirct::pipelinetocalyx::PipelineScheduleable | |
| Ccirct::msft::PlacementDB::PlacementCell | A memory slot |
| Ccirct::msft::PlacementDB | A data structure to contain both the locations of the primitives on the device and instance assignments to said primitives locations, aka placements |
| CPlacementDB | |
| Ccirct::esi::Platform | This should eventually become a set of functions to define the various platform-specific lowerings |
| CPlusArgsTestLowering | |
| CPlusArgsValueLowering | |
| Cesi::detail::PODTypeDeserializer< T > | Default deserializer for simple 1:1 typed reads |
| CPointerLikeTypeTraits | |
| Cllvm::PointerLikeTypeTraits< circt::firrtl::Annotation > | Make Annotation behave like a Attribute in terms of pointer-likeness |
| Cllvm::PointerLikeTypeTraits< circt::llhd::TimeAttr > | |
| Cllvm::PointerLikeTypeTraits< mlir::ArrayAttr > | |
| Cllvm::PointerLikeTypeTraits< circt::CyclicOpSCC > | |
| Cesi::detail::PollingBuffer< BufferedT > | Shared queue/promise helper for polling-style read APIs |
| Cesiaccel.types.Port | |
| Cesiaccel.types.ReadPort | |
| Cesiaccel.types.WritePort | |
| Ccirct::hw::PortConversion | Base class for the port conversion of a particular port |
| Ccirct::hw::PortConversionBuilder | |
| Ccirct::hw::PortConverterImpl | |
| Ccirct::hw::PortConverter< PortConversionBuilderImpl > | |
| Ccirct::calyx::PortInfo | This holds information about the port for either a Component or Cell |
| Ccirct::firrtl::PortInfo | This holds the name and type that describes the module's ports |
| Ccirct::systemc::detail::PortInfo | A struct containing minimal information for a systemc module port |
| Ccirct::ImportVerilog::PortLowering | Port lowering information |
| Ccirct::firrtl::GatedClockConversion::PortPairPlan | (baseClock, enable) port pair to append to a module |
| Ccirct::pretty::PPExtString | String wrapper to indicate string has external storage |
| Ccirct::pretty::PPSaveString | String wrapper to indicate string needs to be saved |
| Ccirct::calyx::PredicateInfo | Predicate information for the floating point comparisons |
| Ccirct::pretty::PrettyPrinter | |
| Ccirct::msft::PrimitiveDB | A data structure to contain locations of the primitives on the device |
| CPrimitiveDB | |
| Ccirct::pretty::PrettyPrinter::PrintEntry | Printing information for active scope, stored in printStack |
| Ccirct::om::evaluator::AttributeValue::PrivateTag | |
| Ccirct::scheduling::Problem | This class models the most basic scheduling problem |
| Ccirct::scheduling::ChainingProblem | This class models the accumulation of physical propagation delays on combinational paths along SSA dependences |
| Ccirct::scheduling::ChainingCyclicProblem | This class models the accumulation of physical propagation delays on combinational paths along SSA dependences on a cyclic scheduling problem |
| Ccirct::scheduling::CyclicProblem | This class models a cyclic scheduling problem |
| Ccirct::scheduling::ChainingCyclicProblem | This class models the accumulation of physical propagation delays on combinational paths along SSA dependences on a cyclic scheduling problem |
| Ccirct::scheduling::ModuloProblem | This class models the modulo scheduling problem as the composition of the cyclic problem and the resource-constrained problem with fully-pipelined shared operators |
| Ccirct::scheduling::SharedOperatorsProblem | This class models a resource-constrained scheduling problem |
| Ccirct::scheduling::ModuloProblem | This class models the modulo scheduling problem as the composition of the cyclic problem and the resource-constrained problem with fully-pipelined shared operators |
| CPyAppIDIndex | |
| Ccirct::python::PyFileAccumulator | Taken from NanobindUtils.h in MLIR |
| CPyLocationVecIterator | |
| Cesi::QueuedDecodeTypeDeserializer< T > | Helper base class for stateful deserializers which may emit zero, one, or many typed outputs for each raw input message |
| Cesi::SerialListTypeDeserializer< T > | Reusable serial-list window deserializer |
| Cesi::QueuedDecodeTypeDeserializer< SerialCoordOutputBatch > | |
| CSerialCoordOutputBatch::TypeDeserializer | |
| Cesi.RandomAccessMemoryDeclOp | |
| Ccirct::ReachableMuxes | |
| Cesi::backends::cosim::RpcClient.Impl::ReadCallbackEntry | |
| Cesi::backends::cosim::RpcClient::ReadChannelConnection | Abstract handle for a read channel connection |
| CRpcClient::ReadChannelConnection | Abstract handle for a read channel connection |
| Csv.ReadInOutOp | |
| Cesi::utils::ReadyIdSet< ID > | Multi-producer / single-consumer dirty-set of channel ids, with CV-style blocking drain semantics |
| Ccirct::firrtl::RecursiveTypeProperties | A collection of bits indicating the recursive properties of a type |
| Ccirct::ReducePatternSet | |
| Ccirct::Reduction | An abstract reduction pattern |
| Ccirct::OpReduction< firrtl::CircuitOp > | |
| CModuleNameSanitizer | Pseudo-reduction that sanitizes module and port names |
| Ccirct::OpReduction< FExtModuleOp > | |
| CExtmoduleConventionRemover | Reduction that removes the convention attribute from external modules |
| Ccirct::OpReduction< ListCreateOp > | |
| CListCreateElementRemover | A reduction pattern that removes elements from FIRRTL list create operations |
| Ccirct::OpReduction< FModuleOp > | |
| CModuleConventionRemover | Reduction that removes the convention attribute from regular modules |
| Ccirct::OpReduction< HWModuleOp > | |
| CModuleExternalizer | A sample reduction pattern that maps hw.module to hw.module.extern |
| Ccirct::OpReduction< mlir::ModuleOp > | |
| CModuleNameSanitizer | Pseudo-reduction that sanitizes module and port names |
| Ccirct::OpReduction< StateOp > | |
| CStateElimination | A sample reduction pattern that converts arc.state operations to the simpler arc.call operation and removes clock, latency, name attributes, enables, and resets in the process |
| CModuleInternalNameSanitizer | Pseudo-reduction that sanitizes the names of operations inside modules |
| CHWConstantifier | A sample reduction pattern that replaces integer operations with a constant zero of their type |
| CHWOperandForwarder< OpNum > | A sample reduction pattern that replaces all uses of an operation with one of its operands |
| CModuleInputPruner | Remove unused module input ports |
| CModuleInternalNameSanitizer | Pseudo-reduction that sanitizes the names of operations inside modules |
| CModuleOutputPruner | Remove unused module output ports |
| CSVNamehintRemover | Pseudo-reduction that removes sv.namehint attributes from operations |
| Ccirct::OpReduction< OpTy > | A reduction pattern for a specific operation |
| Ccirct::PassReduction | A reduction pattern that applies an mlir::Pass |
| CIMDCEPortReduction | |
| Ccirct::FirRegLowering::RegCondition | The conditions under which a register is defined |
| Cesi::services::MMIO::RegionDescriptor | Describe a region (slice) of MMIO space |
| Cesi::registry::internal::RegisterAccelerator< TAccelerator > | |
| Cesi::registry::internal::RegisterEngine< TEngine > | Helper struct to register engines |
| Ccirct::FirRegLowering::RegLowerInfo | |
| Csv.RegOp | |
| CModuleState::Render< T > | |
| CModuleState::RenderLong | |
| Ccirct::comb::ReplExtMatcher< SubType > | |
| Cesi.RequestConnectionOp | |
| CReservedWordsCreator | Return a StringSet that contains all of the reserved names (e.g |
| Ccirct::llhd::deseq::ResetInfo | A single reset extracted from a process during trigger analysis |
| Ccirct::firrtl::impl::ResolveTracesBase | |
| CResolveTracesPass | |
| Ccirct::scheduling::Problem::ResourceType | Resource types are distinguished by name (chosen by the client) |
| Ccirct::synth::ResourceUsageAnalysis::ResourceUsage | Resource usage counts for a set of operations |
| Ccirct::synth::ResourceUsageAnalysis | Analysis that computes resource usage for Synth dialect operations |
| Cmlir::RewritePattern | |
| CReductionCat | |
| CAndRCat | |
| COrRCat | |
| CXorRCat | |
| Ccirct::firrtl::GatedClockConversion::RootRewrite | Root rewrite applied by applyPlan(): clock the op by baseClk and sink enableId into it |
| Cesi::backends::cosim::RpcClient | A client for the cosim RPC server |
| CRpcClient | A client for the cosim RPC server |
| Cesi::cosim::RpcServer | TODO: make this a proper backend (as much as possible) |
| CRpcServer | TODO: make this a proper backend (as much as possible) |
| Ccirct::rtg::RTGOpVisitor< ConcreteType, ResultType, ExtraArgs > | This helps visit TypeOp nodes |
| Cstd::runtime_error | |
| Cesi::AcceleratorMismatchError | |
| CRuntimeError | |
| CPython.support.ConnectionError | |
| CPython.support.UnconnectedSignalError | |
| Ccirct::ImportVerilog::Context::ScanStringResult | Result of converting a scan format string |
| Ccirct::calyx::SchedulerInterface< T > | Holds common utilities used for scheduling when lowering to Calyx |
| Ccirct::calyx::SchedulerInterface< Scheduleable > | |
| Ccirct::pipelinetocalyx::PipelineScheduler | Holds additional information required for scheduling Pipeline pipelines |
| Ccirct::pipelinetocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Ccirct::scftocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| Ccirct::ScopedDebugPassLogger | RAII helper for creating a pass header and footer automatically |
| Cesi::Segment | A contiguous, non-owning view of bytes within a SegmentedMessageData |
| Cesi::SegmentedMessageData | Abstract multi-segment message |
| CSerialCoordBurst | |
| CSerialCoordInput | |
| CSerialCoordInput | |
| Cesi::MessageData | A concrete flat message backed by a single vector of bytes |
| Cesi::SegmentedMessageDataCursor | Cursor for incremental consumption of a SegmentedMessageData |
| Ccirct::scftocalyx::SeqOpLoweringStateInterface | Stores the state information for condition checks involving sequential computation |
| Ccirct::scftocalyx::ComponentLoweringState | Handles the current state of lowering of a Calyx component |
| CSerialCoordData | |
| CSerialCoordHeader | |
| CSerialCoordOutputBatch | Deserialized result batch from the serial coord translator |
| CSerialCoordOutputData | |
| CSerialCoordOutputFrame | |
| CSerialCoordOutputHeader | |
| Cesi::services::Service | Parent class of all APIs modeled as 'services' |
| Cesi::services::CallService | Service for servicing function calls from the accelerator |
| Cesi::services::ChannelService | Service for raw communication channels to/from the accelerator |
| Cesi::services::CustomService | A service for which there are no standard services registered |
| Cesi::services::FuncService | Service for calling functions |
| Cesi::services::HostMem | |
| Cesi::services::MMIO | |
| CTraceMMIO | |
| Cesi::services::SysInfo | Information about the Accelerator system |
| Cesi::services::MMIOSysInfo | Implement the SysInfo API for a standard MMIO protocol |
| Cesi::services::TelemetryService | Service for retrieving telemetry data from the accelerator |
| Ccirct::esi::ServiceGeneratorDispatcher | Class which "dispatches" a service implementation request to its specified generator |
| CServiceGenFunc | Container for a Python function that will be called to generate a service |
| Cesi.ServiceImplementation | |
| Ccustom_channel_service.CustomChannelService | |
| Cesiaccel.bsp.common.ChannelMMIO | |
| Cesiaccel.bsp.common.TelemetryMMIO | |
| Cesi::ServicePortDesc | A description of a service port |
| Ccirct::esi::ServicePortInfo | Describes a service port |
| Cesi::services::ServiceRegistry | Registry of services which can be instantiated directly by the Accelerator class if the backend doesn't do anything special with a service |
| Ccirct::comb::SextByMatcher< SubType > | |
| Ccirct::firrtl::impl::SFCCompatBase | |
| CSFCCompatPass | |
| Ccirct::ExportVerilog::SharedEmitterState | This class tracks the top-level state for the emitters, which is built and then shared across all per-file emissions that happen in parallel |
| Ccomb.ShlOp | |
| Ccomb.ShrSOp | |
| Ccomb.ShrUOp | |
| Ccirct::bmc::BMCTrace::Signal | Metadata for a tracked signal in the trace |
| Ccirct::synth::Signal | Edge representation in the logic network |
| Csimulator.SimProcess | |
| Csimulator.Simulator | |
| Cquesta.Questa | |
| Cverilator.Verilator | |
| Ccirct::SmallDenseMap< KeyT, ValueT, InlineBuckets, KeyInfoT, BucketT > | |
| Cllvm::SmallDenseMap< KeyT, ValueT, InlineBuckets, KeyInfoT, BucketT > | |
| CSmallDenseMap< KeyT, ValueT, InlineBuckets, KeyInfoT, BucketT > | |
| Ccirct::arc::runtime::FmtDescriptor::SmallLiteral | Literal string (small string optimization) |
| Ccirct::SmallMapVector< KeyT, ValueT, N > | |
| Cllvm::SmallMapVector< KeyT, ValueT, N > | |
| CSmallMapVector< KeyT, ValueT, N > | |
| Ccirct::SmallSet< T, N, C > | |
| Cllvm::SmallSet< T, N, C > | |
| Ccirct::SmallSetVector< T, N > | |
| Cllvm::SmallSetVector< T, N > | |
| CSmallSetVector< T, N > | |
| Ccirct::SMTGlobalsHandler | A symbol cache for LLVM globals and functions relevant to SMT lowering patterns |
| Ccirct::synth::impl::SOPBalancingBase | |
| CSOPBalancingPass | |
| Ccirct::SOPForm | Represents a sum-of-products expression |
| Csimulator.SourceFiles | |
| Ccirct::SparseOpSCC< Direction, NumInlineElts > | Iterative Tarjan SCC analysis on a sparse subgraph of MLIR operations |
| Ccirct::SSAMaximizationStrategy | Strategy class to control the behavior of SSA maximization |
| Ccirct::arc::StateInfo | Gathers information about a given Arc state |
| Cfsm.StateOp | |
| Cmlir::StdExprVisitor< ConcreteType, ResultType, ExtraArgs > | StdExprVisitor is a visitor for standard expression nodes |
| Ccirct::firrtl::StmtExprVisitor< ConcreteType, ResultType, ExtraArgs > | StmtExprVisitor is a visitor for FIRRTL operation that has an optional result |
| Ccirct::firrtl::StmtExprVisitor< ConcreteType, void, ExtraArgs... > | |
| Ccirct::firrtl::FIRRTLVisitor< ConcreteType, ResultType, ExtraArgs > | FIRRTLVisitor allows you to visit all of the expr/stmt/decls with one class declaration |
| Ccirct::firrtl::StmtVisitor< ConcreteType, ResultType, ExtraArgs > | ExprVisitor is a visitor for FIRRTL statement nodes |
| Ccirct::hw::StmtVisitor< ConcreteType, ResultType, ExtraArgs > | This helps visit TypeOp nodes |
| Ccirct::firrtl::StmtVisitor< ConcreteType, void, ExtraArgs... > | |
| Ccirct::firrtl::FIRRTLVisitor< ConcreteType, ResultType, ExtraArgs > | FIRRTLVisitor allows you to visit all of the expr/stmt/decls with one class declaration |
| CStreamingAddArg | Packed struct representing a parallel window argument for StreamingAdder |
| CStreamingAddResult | Packed struct representing a parallel window result for StreamingAdder |
| CStreamingAddTranslatedArg | Test the StreamingAdder module using message translation |
| CStreamingAddTranslatedResult | Translated result struct for StreamingAdder |
| Ccirct::StringAttrOrRef | A helper union that can represent a StringAttr, StringRef, or Twine |
| Ccirct::ExportVerilog::StringOrOpToEmit | This class wraps an operation or a fixed string that should be emitted |
| CStruct | |
| Cesiaccel.bsp.xrt.AXI_Lite_Read_Resp | |
| Cesiaccel.bsp.xrt.MMIOIntermediateCmd | |
| Cesiaccel.bsp.xrt.MMIOSel | |
| Cloopback.ArgStruct | |
| Cloopback.OddInner | |
| Cloopback.OddStruct | |
| Cloopback.ResultStruct | |
| Cserialization_probes.BitPackArg | |
| Cserialization_probes.BitPackResult | |
| Cserialization_probes.PackStruct | |
| Cserialization_probes.SignResult | |
| Cserialization_probes.SignResult13 | |
| Ctest_codegen.AckArgs | |
| Ctest_codegen.EventStruct | |
| Ctest_codegen.NotifyArgs | |
| Ctest_codegen.OddInner | |
| Ctest_codegen.OddStruct | |
| Ctest_codegen.StructArgs | |
| Ctest_codegen.StructResult | |
| Ctest_codegen.TransformListItem | |
| Chw.StructCreateOp | |
| Chw.StructExtractOp | |
| Ccirct::moore::StructLikeMember | A member of a struct |
| CStructuralHasher | |
| CStructuralHasherSharedConstants | This struct contains constant string attributes shared across different threads |
| CStructuralHashKey | A struct that represents the key used for structural hashing |
| Ccomb.SubOp | |
| Chwarith.SubOp | |
| Csv.SVVerbatimModuleOp | |
| Csv.SVVerbatimSourceOp | |
| Cdetail::SymbolCache | A utility doing lazy construction of SymbolTables and SymbolUserMaps, which is handy for reductions that need to look up a lot of symbols |
| Ccirct::SymbolCacheBase | Base symbol cache class to allow for cache lookup through a pointer to some abstract cache |
| Ccirct::SymbolCache | Default symbol cache implementation; stores associations between names (StringAttr's) to mlir::Operation's |
| Ccirct::hw::HWSymbolCache | This stores lookup tables to make manipulating and working with the IR more efficient |
| Ccirct::firrtl::TargetToken | Stores an index into an aggregate |
| Ccirct::msft::TclEmitter | Instantiate for all Tcl emissions |
| Ctests.integration.test_backpressure.TestBackpressure | |
| Ccirct::TestCase | A single test case to be run by a tester |
| Ctests.integration.test_channel_arbiter.TestChannelArbiterCosim | |
| Ctest_verilator.TestCompileCommands | |
| Ctest_macro_definitions.TestCosimCliMacroDefinitions | |
| Ctests.integration.test_esitester.TestCosimEsitester | |
| Ctests.integration.test_esitester.TestCosimEsitesterDma | |
| Ccirct::Tester | A testing environment for reduction attempts |
| Ctest_verilator.TestFindVerilatorRoot | |
| Ctests.integration.test_hostmem_read.TestHostMemRead2048 | |
| Ctests.integration.test_hostmem_read.TestHostMemRead4096 | |
| Ctests.integration.test_hostmem_read.TestHostMemRead512 | |
| Ctests.integration.test_hostmem_read.TestHostMemRead8 | |
| Ctests.integration.test_hostmem_read.TestHostMemReadFourOutstanding | |
| Ctests.integration.test_hostmem_read.TestHostMemReadOneOutstanding | |
| Ctests.integration.test_hostmem_write.TestHostMemWrite2048 | |
| Ctests.integration.test_hostmem_write.TestHostMemWrite4096 | |
| Ctests.integration.test_hostmem_write.TestHostMemWrite512 | |
| Ctests.integration.test_hostmem_write.TestHostMemWrite8 | |
| Ctests.integration.test_hostmem_write.TestHostMemWriteDefault | |
| Ctest_macro_definitions.TestLoadMacroDefinitions | |
| Ctests.integration.test_loopback_cpp.TestLoopback | |
| Ctest_verilator.TestMakeFallback | |
| Ctest_macro_definitions.TestPytestMacroDefinitions | |
| Ctest_verilator.TestRunCommand | |
| Ctests.integration.test_serialization_probes.TestSerializationProbes | |
| Ctest_verilator.TestSimulatorDiscovery | |
| Ctest_verilator.TestWriteCmake | |
| Ccirct::firrtl::TieOffCache | Helper class to cache tie-off values for different FIRRTL types |
| Ccirct::pretty::Token | |
| Ccirct::pretty::TokenBase< BeginToken, Token::Kind::Begin > | |
| Ccirct::pretty::BeginToken | |
| Ccirct::pretty::TokenBase< BreakToken, Token::Kind::Break > | |
| Ccirct::pretty::BreakToken | |
| Ccirct::pretty::TokenBase< CallbackToken, Token::Kind::Callback > | |
| Ccirct::pretty::CallbackToken | |
| Ccirct::pretty::TokenBase< EndToken, Token::Kind::End > | |
| Ccirct::pretty::EndToken | |
| Ccirct::pretty::TokenBase< StringToken, Token::Kind::String > | |
| Ccirct::pretty::StringToken | Token types |
| Ccirct::pretty::TokenBase< DerivedT, DerivedKind > | Helper class to CRTP-derive common functions |
| Ccirct::firrtl::TokenAnnoTarget | The parsed annotation path |
| Ccirct::pretty::TokenBuilder< PPTy > | Add convenience methods for generating pretty-printing tokens |
| Ccirct::pretty::TokenBuilder< PPTy > | |
| Ccirct::pretty::TokenStream< PPTy > | |
| Ccirct::pretty::TokenBuilder< PrettyPrinter > | |
| Ccirct::pretty::TokenStream< PrettyPrinter > | |
| Ccirct::pretty::TokenStreamWithCallback< CallableType, DataType, PPTy > | Wrap the TokenStream with a helper for CallbackTokens, to record the print events on the stream |
| Ccirct::pretty::TokenStream< PPTy > | Wrap a PrettyPrinter with TokenBuilder features as well as operator<<'s |
| Ccirct::pretty::Token::TokenInfo | |
| Ccirct::pretty::Token::BeginInfo | |
| Ccirct::pretty::Token::BreakInfo | |
| Ccirct::pretty::Token::CallbackInfo | |
| Ccirct::pretty::Token::EndInfo | |
| Ccirct::pretty::Token::StringInfo | |
| Ccirct::arc::runtime::impl::TraceBuffer | A heap allocated buffer containing raw trace data and time step markers |
| Ccirct::arc::runtime::impl::TraceBufferMarker | Helper for marking time steps within a trace buffer |
| Ccirct::arc::runtime::impl::TraceEncoder | Abstract TraceEncoder managing trace buffers and the encoder thread |
| Ccirct::arc::runtime::impl::DummyTraceEncoder | Dummy encoder discarding all produced trace data |
| Ccirct::arc::runtime::impl::FSTTraceEncoder | Trace buffer encoder producing an FST file |
| Ccirct::arc::runtime::impl::VCDTraceEncoder | Trace buffer encoder producing a VCD file |
| Ccirct::synth::TrackedSpecificBumpPtrAllocator< T > | |
| Cmlir::OpTrait::TraitBase | |
| Ccirct::NonProceduralOp< ConcreteType > | Signals that an operation must not be in a procedural region |
| Ccirct::NonProceduralRegion< ConcreteType > | Signals that an operation's regions are non-procedural |
| Ccirct::ProceduralOp< ConcreteType > | Signals that an operation must not be in a non-procedural region |
| Ccirct::ProceduralRegion< ConcreteType > | Signals that an operation's regions are procedural |
| Ccirct::axi4::OpTrait::PortResultsAtMostOneUse< ConcreteType > | Constrains an op's !axi4.port results to at most one use each |
| Ccirct::calyx::Combinational< ConcreteType > | Signals that the following operation is combinational |
| Ccirct::calyx::ControlLike< ConcreteType > | Signals that the following operation is "control-like." |
| Ccirct::esi::OperatesOnESITypes< ConcreteType > | Trait marking an ESI op that operates on ESI types (e.g |
| Ccirct::firrtl::SameOperandsIntTypeKind< ConcreteOp > | A binary operation where the operands have the same integer kind |
| Ccirct::rtg::InstructionOpAdaptorTrait< ConcreteType > | |
| Ccirct::sv::VendorExtension< ConcreteType > | This class provides a verifier for ops that are expecting their parent to be one of the given parent ops |
| Cmlir::OpTrait::HasClock< ConcreteType > | |
| Cmlir::OpTrait::HasParentInterface< InterfaceType >::Impl< ConcreteType > | |
| Cmlir::OpTrait::InnerRefNamespace< ConcreteType > | This trait is for operations that define a scope for resolving InnerRef's, and provides verification for InnerRef users (via InnerRefUserOpInterface) |
| Cmlir::OpTrait::InnerSymbolTable< ConcreteType > | A trait for inner symbol table functionality on an operation |
| Cmlir::TypeTrait::TraitBase | |
| Ccirct::firrtl::WidthQualifiedTypeTrait< IntType > | |
| Ccirct::firrtl::IntType | This is the common base class between SIntType and UIntType |
| Ccirct::firrtl::WidthQualifiedTypeTrait< ConcreteType > | Trait for types which have a width |
| Cfsm.TransitionOp | |
| Cesi::ChannelPort::TranslationInfo | Instructions for translating windowed types |
| CTriggeredLowering | |
| Cstd::true_type | |
| CHasParameters< Properties, std::void_t< decltype(std::declval< Properties >().parameters)> > | |
| Cesi::detail::has_type_deserializer< T, std::void_t< typename T::TypeDeserializer > > | |
| Cesi::is_std_array< std::array< T, N > > | |
| Ccirct::llhd::deseq::TruthTable | A boolean function expressed as a truth table |
| Cesi::utils::TSQueue< T > | Thread safe queue |
| CTVpiVecval | |
| Cesi::Type | Root class of the ESI type system |
| Cesi::AnyType | The "any" type is a special type which can be used to represent any type, as identified by the type id |
| Cesi::ArrayType | Arrays have a compile time specified (static) size and an element type |
| Cesi::BitVectorType | Bit vectors include signed, unsigned, and signless integers |
| Cesi::BitsType | Bits are just an array of bits |
| Cesi::IntegerType | Integers are bit vectors which may be signed or unsigned and are interpreted as numbers |
| Cesi::SIntType | Signed integer |
| Cesi::UIntType | Unsigned integer |
| Cesi::BundleType | Bundles represent a collection of channels |
| Cesi::ChannelType | Channels are the basic communication primitives |
| Cesi::ListType | Lists represent variable-length sequences of elements of a single type |
| Cesi::StructType | Structs are an ordered collection of fields, each with a name and a type |
| Cesi::TypeAliasType | Type aliases provide a named type which forwards to an inner type |
| Cesi::UnionType | Unions contain one active field without storing a tag |
| Cesi::VoidType | The "void" type is a special type which can be used to represent no type |
| Cesi::WindowType | Windows represent a fixed-size sliding window over a stream of data |
| Cmlir::Type | |
| Ccirct::llhd::WrapperType | Common base of types wrapping a nested type |
| Cnanobind::detail::type_caster< std::any > | Nanobind doesn't have a built-in type caster for std::any |
| Cnanobind::detail::type_hook< ChannelPort > | |
| Cnanobind::detail::type_hook< Service > | |
| CFIRRTLType::TypeBase | |
| Ccirct::firrtl::FIRRTLBaseType | |
| Ccirct::firrtl::IntType | This is the common base class between SIntType and UIntType |
| Cmlir::Type::TypeBase | |
| Ccirct::firrtl::BaseTypeAliasOr< BaseTy > | |
| Ccirct::hw::TypeAliasOr< BaseTy > | |
| Ccirct::hw::TypeVariant< Types > | Utility type that wraps a type that may be one of several possible Types |
| CType::TypeBase | |
| Ccirct::systemc::BigIntType | Represents a finite word-length signed integer in SystemC as described in IEEE 1666-2011 §7.6.5 |
| Ccirct::systemc::BigUIntType | Represents a finite word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7.6.6 |
| Ccirct::systemc::BitVectorBaseType | Represents a finite word-length bit vector in SystemC as described in IEEE 1666-2011 §7.9.3 |
| Ccirct::systemc::BitVectorType | Represents a finite word-length bit vector in SystemC as described in IEEE 1666-2011 §7.9.5 |
| Ccirct::systemc::IntBaseType | Represents a limited word-length signed integer in SystemC as described in IEEE 1666-2011 §7.5.2 |
| Ccirct::systemc::IntType | Represents a limited word-length signed integer in SystemC as described in IEEE 1666-2011 §7.5.4 |
| Ccirct::systemc::LogicVectorBaseType | Represents a finite word-length bit vector in SystemC as described in IEEE 1666-2011 §7.9.4 |
| Ccirct::systemc::LogicVectorType | Represents a finite word-length bit vector (of four-state values) in SystemC as described in IEEE 1666-2011 §7.9.6 |
| Ccirct::systemc::SignedType | Represents a finite word-length signed integer in SystemC as described in IEEE 1666-2011 §7.6.3 |
| Ccirct::systemc::UIntBaseType | Represents a limited word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7.5.3 |
| Ccirct::systemc::UIntType | Represents a limited word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7.5.5 |
| Ccirct::systemc::UnsignedType | Represents a finite word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7.6.4 |
| Ccirct::TypeConverter | |
| Ccirct::HWArithToHWTypeConverter | A helper type converter class that automatically populates the relevant materializations and type conversions for converting HWArith to HW |
| Cmlir::TypeConverter | |
| Ccirct::HWArithToHWTypeConverter | A helper type converter class that automatically populates the relevant materializations and type conversions for converting HWArith to HW |
| Cesi::TypedCallback< ArgT, ResultT, SkipTypeCheck > | |
| Cesi::TypedCallback< ArgT, void, SkipTypeCheck > | Partial specialization: typed argument, void result |
| Cesi::TypedCallback< void, ResultT, SkipTypeCheck > | Partial specialization: void argument, typed result |
| Cesi::TypedCallback< void, void, SkipTypeCheck > | Full specialization: void argument, void result |
| Chw.TypedeclOp | |
| Cesi::TypedFunction< ArgT, ResultT, SkipTypeCheck > | |
| Cesi::TypedFunction< ArgT, void, SkipTypeCheck > | Partial specialization: typed argument, void result |
| Cesi::TypedFunction< void, ResultT, SkipTypeCheck > | Partial specialization: void argument, typed result |
| Cesi::TypedFunction< void, void, SkipTypeCheck > | Full specialization: void argument, void result |
| Cesi::TypedReadPort< T, SkipTypeCheck > | Strongly typed wrapper around a raw read channel |
| Cesi::TypedReadPort< void > | Specialization for void — read discards data and returns nothing |
| Cesi::TypedWritePort< T, SkipTypeCheck > | |
| Cesi::TypedWritePort< void > | Specialization for void — write takes no data argument |
| Ccirct::hw::TypeOpVisitor< ConcreteType, ResultType, ExtraArgs > | This helps visit TypeOp nodes |
| Chw::TypeOpVisitor | |
| CEmittedExpressionStateManager | This class handles information about AST structures of each expressions |
| Chw.TypeScopeOp | |
| Ccirct::TypeStorage | |
| Ccirct::firrtl::detail::ClassTypeStorage | |
| Ccirct::firrtl::detail::FIRRTLBaseTypeStorage | |
| Ccirct::firrtl::detail::BaseTypeAliasStorage | |
| Ccirct::firrtl::detail::BundleTypeStorage | |
| Ccirct::firrtl::detail::FEnumTypeStorage | |
| Ccirct::firrtl::detail::FVectorTypeStorage | |
| Ccirct::firrtl::detail::WidthTypeStorage | |
| Ccirct::firrtl::detail::OpenBundleTypeStorage | |
| Ccirct::firrtl::detail::OpenVectorTypeStorage | |
| Ccirct::sim::detail::DPIFunctionTypeStorage | |
| Cmlir::TypeStorage | |
| Ccirct::firrtl::detail::ClassTypeStorage | |
| Ccirct::firrtl::detail::FIRRTLBaseTypeStorage | |
| Ccirct::firrtl::detail::OpenBundleTypeStorage | |
| Ccirct::firrtl::detail::OpenVectorTypeStorage | |
| Ccirct::sim::detail::DPIFunctionTypeStorage | |
| CTypeStorage | |
| Ccirct::hw::detail::ModuleTypeStorage | |
| Ccirct::systemc::detail::IntegerWidthStorage | Integer Type Storage and Uniquing |
| Cllvm::detail::TypeSwitchBase | |
| Ccirct::firrtl::FIRRTLTypeSwitch< T, void > | Specialization of FIRRTLTypeSwitch for void returning callables |
| Ccirct::firrtl::FIRRTLTypeSwitch< T, ResultT > | This class implements the same functionality as TypeSwitch except that it uses firrtl::type_dyn_cast for dynamic cast |
| Ccirct::firrtl::FIRRTLTypeSwitch< T, void > | Specialization of FIRRTLTypeSwitch for void returning callables |
| Ccirct::UnusedOpPruner | Utility that tracks operations that have potentially become unused and allows them to be cleaned up at a later point |
| Ccirct::llhd::deseq::ValueEntry | A single entry in a value table |
| Ccirct::llhd::deseq::ValueField | Identify a specific subfield (or the whole) of an SSA value using the HW field ID scheme |
| Ccirct::ValueMapper | Facilitates the definition and connection of SSA def-use chains between two location - a 'from' location (defining use-def chains) and a 'to' location (where new operations are created based on the 'from' location) |
| Ccirct::llhd::deseq::ValueTable | A table of SSA values and the conditions under which they appear |
| Ccirct::synth::ValueWithArrivalTime | Helper class for delay-aware tree building |
| Csv.VarAssignOp | |
| Csv.VarOp | |
| Ccirct::arc::runtime::impl::VCDSignalId | String identifier for a signal in a VCD file consisting of characters in the ASCII range from '! |
| Ccirct::arc::runtime::impl::VCDSignalTableEntry | A traced signal in the VCD file |
| Cstd::vector | |
| Cesi::AppIDPath | |
| Ccirct::lsp::VerilogDocument | |
| Ccirct::lsp::VerilogIndex | |
| Ccirct::lsp::VerilogServer | This class implements all of the Verilog related functionality necessary for a language server |
| Ccirct::lsp::VerilogServerContext | |
| Ccirct::lsp::VerilogServerOptions | |
| Ccirct::lsp::VerilogTextFile | This class represents a text file containing one or more Verilog documents |
| Ccirct::ImportVerilog::VirtualInterfaceLowering | Cached lowering information for representing SystemVerilog virtual
interface handles as Moore types (a struct of references to interface members) |
| Ccirct::ImportVerilog::VirtualInterfaceMemberAccess | A mapping entry for resolving Slang virtual interface member accesses |
| Ccirct::ltl::Visitor< ConcreteType, ResultType, ExtraArgs > | |
| Ccirct::sv::Visitor< ConcreteType, ResultType, ExtraArgs > | |
| Ccirct::verif::Visitor< ConcreteType, ResultType, ExtraArgs > | |
| Csv::Visitor | |
| CEmittedExpressionStateManager | This class handles information about AST structures of each expressions |
| Ctest_codegen.VoidComms | |
| Ccirct::msft::PlacementDB::WalkOrder | |
| Ccirct::scftocalyx::WhileScheduleable | |
| Cesi::WireInfo | Compute the wire byte count for a port type |
| CWireLowering | |
| Csv.WireOp | |
| Ccirct::firrtl::GatedClockConversion::WirePairPlan | Temporary (base clock, enable) carrier wires at the top of mod, standing in for a wire/node alias of a gated clock |
| Ccirct::firrtl::WiringProblem | A representation of a deferred Wiring problem consisting of a source that should be connected to a sink |
| Cesi::backends::cosim::RpcClient.Impl::WriteCredit | |
| Ccomb.XorOp | |
| Ccirct::comb::ZextByMatcher< SubType > | |
| CCallableType & | |
| CDenseMap< mlir::Block *, SmallVector< Scheduleable > > | |
| CDenseMap< Operation *, calyx::GroupOp > | |
| CDenseMap< Operation *, DenseMap< unsigned, calyx::RegisterOp > > | |
| CDenseMap< Operation *, SmallVector< calyx::GroupOp > > | |
| CForOp | |
| CLoopSchedulePipelineOp | |
| Cqueue< DataType > | |
| Cqueue< esi::MessageData > | |
| CRewritePatternSet | |
| Ccirct::ConversionPatternSet | Extension of RewritePatternSet that allows adding matchAndRewrite functions with op adaptors and ConversionPatternRewriter as patterns |
| CSpecificBumpPtrAllocator< circt::synth::Cut > | |
| CSpecificBumpPtrAllocator< circt::synth::CutSet > | |
| CType | |
| Ccirct::firrtl::FIRRTLType | |
| Ccirct::firrtl::PropertyType | |
| Ccirct::moore::UnpackedType | An unpacked SystemVerilog type |
| Ccirct::moore::PackedType | A packed SystemVerilog type |
| Ccirct::moore::WrapperType | |
| Ccirct::systemc::ValueBaseType | This provides a common base class for all SystemC integers |
| CWhileOp | |
1.15.0